Well, it generates a circuit detecting if the input (unsigned 8bit number range [0,255])
can be divided by 3 (can be easily modified to 5,7,etc.) evenly.
If yes, a flag (1 clk cycle) will appear.
Of course one can use modulo ('%' in verilog) to implement the function,
but the cost may be higher.
Consider A = 4'b1011, which is 11 in decimal, let's do this:
X[0] == 2^0 = 1; 1%3 = 1; so there is a 1.
X[1] == 2^1 = 2; 2%3 = 2; so there is a 2.
X[2] == 2^2 = 4; 4%3 = 1; so there is a 1.
X[3] == 2^3 = 8; 8%3 = 2; so there is a 2.
Let's add the due remainders up, which is
A[0]*X[0] + A[1]*X[1] + A[2]*X[2] + A[3]*X[3] = 5,
and 5 is not a multiple of 3.
Try 4'b0011 or 4'b1111, you will see it.
If you have a better solution (in terms of RTL implementation), do tell me!
I hereby thank you in advance.
Guo Yu
module div3
( input clk,
input rst_n,
input [7:0] data,
output reg flag
);
reg [3:0] sum;
integer i;
always @ *
begin
sum = 0;
for (i=0;i<8;i=i+1)
begin
if (i==0 || i==2 || i==4 || i==6 )
sum = (data[i]) ? sum + 1 : sum;
else
sum = (data[i]) ? sum + 2 : sum;
end
end
always @ (posedge clk, negedge rst_n)
begin
if (!rst_n)
flag <= 1'b0;
else if (sum ==0 || sum ==3 || sum==6 || sum==9 || sum==12)
Just work hard on it. You will find it is very useful.作者: guoyu 时间: 2010-10-1 11:27
增加了Testbench.作者: zhang2000 时间: 2010-10-1 21:00
给你改进一下，每两个bit 进行组合译码
X[7] X[6] 分成一组
X[5] X[4] 分成一组
X[3] X[2] 分成一组
X[1] X[0] 分成一组