Job Scopes & Responsibilities
1. Graduate or Master degree in Electronics Engineering
2. Minimum 2 years, preferrably with 3 years IC/SoC Design experience
3. Solid working experience and knowledge in Verilog/VHDL, SystemVerilog,
C, SystemC
4. Experience in both design and verification aspects
5. Good working experience and knowledge in SoC Design tool flow and tool
usage (Cadence, Synopsys, Mentor, etc …)
6. Be ready to work outside normal working hour
7. Be prepare to be assigned to either Beijing or Shanghai office
8. May require to work at customer site for prolong period as job
required
9. Good people commuication skill
10. Provide pre-sales and post-sales technical presentation and support
11. Good English reading and writing ability
