assign DATA=(link_bus)?DATAOUT:16'hzzzz;
//---------------------
//assign DATA=DATAOUT;
//---------------------
reg [25:0]cnt;
always@(posedge clk) begin
cnt<=cnt+1;
end
assign led=cnt[25];
reg [15:0]ram,ram2;
always@(nWE or nCS or ADDR) begin
if((nCS==0)&&(nWE==0)) begin
case(ADDR)
16'h55: begin ram<=DATA; end
16'h77: begin ram2<=DATA; end
default:begin end
endcase
end
end
always@(nOE or nCS or ADDR) begin
if((nCS==0)&&(nOE==0)) begin
case(ADDR)
16'h66: begin DATAOUT<=ram; end
16'h88: begin DATAOUT<=ram2; end
default: begin end
endcase
end
else begin
DATAOUT<=16'hzzzz;
end
end
endmodule作者: weizhiheng 时间: 2010-4-17 22:56 本帖最后由 weizhiheng 于 2010-4-18 08:53 编辑
