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标题: 上海恒原内部推荐职位 [打印本页]

作者: loisfun 时间: 2008-10-29 10:15
标题: 上海恒原内部推荐职位
上海恒原是一家今年刚成立的公司，具体情况详见www.panovel.com
职位名称：模拟/混合信号电路设计工程师
1．职责
(1) 参加模拟和混合信号集成电路开发的各项工作；
(2) 产品功能定义和框架结构确定；
(3) 对竞争对手的现有产品和潜在新产品作功能性能和优势劣势评估；
(4) 研究用于新一代产品的技术；
(5) 基于已有技术开发新的技术和产品；
(6) 器件级和系统级的仿真和设计确认；
(7) 支持‘片上系统’（SoC）的功能块集成、版图设计和验证；
(8) 原型样品芯片的评估；
(9) 支持测试系统的开发；
(10) 产品发布；
2．资格
(1) 在Bipolar and CMOS 工艺方面具有坚实知识基础；
(2) 具有对模拟集成电路进行测试和构建测试环境的能力；
(3) 在基本的模拟/混合信号电路方面具备设计CMOS器件模型、各种放大器、比较器、参考电压、数据转换器频率补偿；
(4) 熟悉Cadence 设计工具和UNIX操作系统；
(5) 出色的书面和口头沟通能力。
3．优先考虑:
模拟/混合信号电路专业的硕士或博士。

Position title: Analog / Mixed-signal Engineer
1． Responsibilities
(1) Participate in all aspects of the development of analog and mixed signal integrated circuits;
(2) Product definition and architectural development;
(3) The evaluation of capabilities, strengths and weaknesses against competitors for existing products and for potential new products;
(4) Carry out research to establish technology concepts required to deliver future anticipated products;
(5) Developing new technologies and new products deriving from existing technologies;
(6) System and component level simulation and design validation;
(7) Support of SoC IP integration, layout and verification;
(8) Prototype evaluation;
(9) Support of test development;
(10) Product release.
2． Qualification:
(1) Good knowledge of Bipolar and CMOS technology;
(2) Competence in analog circuit measurement and construction techniques;
(3) Design knowledge in areas of fundamental Analog/Mixed-signal circuits CMOS device model, various amplifiers (rail-to-rail, folded-cascode, fully differential), comparator, voltage reference, data converters frequency compensation;
(4) Familiarity with Cadence design tools, UNIX O/S;
(5) Excellent written and verbal communication skills.
3． Priority:
MSEE or PhD in the Mixed signal design.

职位名称：物理层ASIC设计工程师
1．职责：
(1) 与‘物理层系统工作组’合作提出物理层ASIC框图架构；
(2) 物理层算法的ASIC实现；
(3) 与‘MAC工作组’和‘固件组’合作完成‘物理层-MAC’接口；
(4) 物理层的FPGA验证和排错。
2．资格：
(1) OFDM物理层实现的直接工作经验；
(2) OFDM物理层优化和排错的直接工作经验；
(3) 在ASIC设计流程，包括时序等方面有丰富经验。
3．优先考虑:
有FPGA实现，无线通信IC设计经验者；硕士或以上学历。

Position title: Phy ASIC Engineer
1． Responsibilities:
(1) Work with PHY system group to come up with PHY ASIC block architecture;
(2) ASIC implementation of PHY algorithm;
(3) Work with MAC and Firmware groups for PHY-MAC interface;
(4) FPGA validation and debugging of PHY algorithms;
2．Qualification:
(1) Hands on experience on OFDM PHY implementation;
(2) Hands on experience on OFDM PHY optimization and debugging;
(3) Solid experience on ASIC flow, including timing closure.
3． Priority:
(1) FPGA mapping capability;
(2) Wireless communication IC design experience;
(3) MS and higher.

职位名称：SoC ASIC 设计工程师
1．职责
(1) 在UWB片上系统(SoC)上集成ARM处理器和AMBA总线；
(2) 设计DMA；
(3) 实现MAC功能，如排队管理；
(4) 与‘物理层ASIC工作组’和‘固件工作组’合作完成‘物理层-MAC’接口。
2．资格
(1) 具有SoC设计的丰富经验；
(2) 具有ASIC设计流程的丰富；
(3) 具有ARM/AMBA集成的经验；
(4) 具有DMA设计经验；
(5) 在复杂FIFO管理方面有经验。
3．优先考虑:
有以下经验者：ARM 集成，AMBA总线，DMA和MAC；硕士或以上学位。

Position title: SoC ASIC Engineer
1． Responsibilities:
(1) Integration of ARM processor and AMBA bus for UWB SoC;
(2) Design of DMAs;
(3) Implementation of MAC functions such as queue management;
(4) Work with PHY ASIC group and Firmware group on PHY-MAC interface.
2． Qualification:
(1) Solid experience on SoC design;
(2) Solid experience in ASIC flow;
(3) Experience of ARM/AMBA integration;
(4) Experience of DMA design;
(5) Experience of complicated FIFO management.
3． Priority:
(1) ARM integration experience;
(2) AMBA bus experience;
(3) DMA experience
(4) MAC experience;
(5) MS and higher.

职位名称：RF集成电路设计工程师
1．职责
(1) 参加RF集成电路开发的各项工作；
(2) 产品功能定义和框架结构确定；
(3) 器件级和系统级的仿真和设计确认；
(4) 支持‘片上系统’（SoC）的功能块集成、版图设计和验证。
2．资格
(1) 能够在晶体管级设计一种或多种下列单元LNA, Mixer, RFVGA, VCO, 综合器；
(2) 充分了解物理版图需求，能够完成关键的版图设计；
(3) 对IC设计CAD工具，如Spectre, ADS, Matlab等，具有扎实知识；
(4) 了解RF系统和通信系统；
(5) 具备实验室测试能力，能够对照设计规范评估原型样品。
3．优先考虑:
RFIC专业的硕士或博士。

Position title: RFIC Engineer
1． Responsibilities:
(1) Participate in all aspects of the development of RF integrated circuits;
(2) Product definition and architectural development;
(3) System and component level simulation and design validation;
(4) Support of SoC IP integration, layout and verification;
2． Qualification:
(1) In transistor-level design of one or more of the following areas are required: LNA, Mixer, RFVGA, VCO, synthesizer;
(2) Thorough understanding of the physical layout requirement and ability to perform critical layouts;
(3) Strong knowledge on IC design CAD tools such as Spectre, ADS, Matlab, etc;
(4) Understanding RF system and communication system;
(5) Lab testing skills to evaluate the prototype unit to the design specification.
3． Priority:
MSEE or PhD in the design of RFICs.

职位名称：通信系统工程师
1．职责：
(1) 用C/C++开发UWB(OFDM)接收端的核心算法；
(2) 完成对性能、复杂度和存储空间需求的仿真和优化；
(3) 完成定点的C优化；
(4) 与‘物理层ASIC工作组’合作提出物理层ASIC架构。
2．资格：
(1) 具有开发OFDM系统算法的丰富经验；
(2) 精通C/C++/Matlab编程；
(3) 透彻理解通信系统；
(4) 具有物理层FPGA/ASIC实现的经验。
3．优先考虑：
有以下经验者：无线通信，定点优化，FPGA实现，物理层ASIC模块架构；博士学位。

Position title: Communication System Engineer
1． Responsibilities:
(1) Develop core algorithms in C/C++ for UWB (OFDM) receiver;
(2) Perform simulation tasks and optimization in performance, complexity and memory requirement;
(3) Perform fixed point C optimization;
(4) Come up with PHY ASIC architecture with PHY ASIC group.
2． Qualification:
(1) Solid experience in OFDM system algorithm development;
(2) Proficient in C/C++/Matlab programming;
(3) Thorough understanding of communication system;
(4) Experience in FPGA/ASIC implementation of PHY.
3． Priority:
(1) Wireless communication experience;
(2) Fixed point optimization experience;
(3) FPGA mapping experience;.
(4) PHY ASIC micro architecture experience;
(5) Ph.D.

职位名称：WINDOWS / LINUX 驱动开发工程师
1．职责
(1) 设计及编写产品和测试驱动软件.
(2) 参与定义无线通讯产品的功能及软件构架.
(3) 了解并实现系统和应用的软件界面.
(4) 参与建立收集和分析芯片性能数据的测试环境.
(5) 协助主管制定详细工作计划.
(6) 致力于解决现存技术问题并积极提供创新思路.
2．资格
(1) 计算机学士学位或同等学历.
(2) 2-5年WINDOWS或LINUX驱动编写经验.
(3) 良好设计和编程能力.
(4) 有PCI驱动开发经验.
(5) 能够与不同部门合作并同时处理多个项目的需求.
(6) 有调试硬件的经验和能力.
(7) 能够适应有压力的工作环境.
3．优先考虑:
硕士以上学历和有USB驱动开发经验的候选人.

Position title: Device Driver Developer
1． Responsibilities:
(1) To define and implement production and testing device drivers on Windows or Linux platforms.
(2) To help in the specification and implementation of wireless communication product features.
(3) To understand Hardware Specs and translate them into device driver development plans.
(4) To help to create infrastructure to gather and analyze chip performance.
(5) To establish work break down schedules with management teams.
(6) To proactively work with other engineers to solve problems and to design solutions/features.
2． Qualifications:
(1) BS in Computer Science or equivalent.
(2) 2-5 years device driver development and delivery responsibilities.
(3) Proven coding and design skills.
(4) 2+ years of PCI device driver development experience.
(5) Ability to coordinate aspects of development across multiple teams and multiple projects.
(6) Ability to troubleshoot hardware related problems.
(7) Ability and energy to make decisions under pressure.
3． Preferences:
(1) Experience in USB device driver development preferred.
(2) M.S. and higher degree preferred.

职位名称：固件开发工程师
1．职责
(1) 设计及编写产品和测试固件；
(2) 参与定义无线通讯产品的功能及软件构架；
(3) 了解并实现芯片的软件界面；
(4) 建立收集和分析芯片性能数据的测试环境；
(5) 协助主管制定详细工作计划；
(6) 致力于解决现存技术问题并积极提供创新思路。
2．资格
(1) 计算机学士学位或同等学历；
(2) 2-5年固件编写经验；
(3) 良好设计和编程能力；
(4) 有RTOS应用知识；
(5) 有BSP应用知识；
(6) 能够与不同部门合作并同时处理多个项目的需求；
(7) 有调试硬件的经验和能力；
(8) 能够适应有压力的工作环境。
3．优先考虑:
具有无线通讯背景者；硕士或以上学历。

Position title: Firmware engineer
1． Responsibilities:
(1) To define and implement low level firmware production and test code that run on SoC systems;
(2) To help in the specification and implementation of wireless communication product features;
(3) To understand high-level chip specifications and translate them into firmware development plans;
(4) To create infrastructure to gather and analyze chip performance;
(5) To establish work break down schedules with management teams;
(6) Proactively work with other engineers to solve problems and to design solutions/features;
2． Qualifications:
(1) BS in Computer Science or equivalent;
(2) 2-5 years software or embedded systems development and delivery responsibilities;
(3) Proven coding and design skills;
(4) Working knowledge of RTOS;
(5) Working knowledge of BSP;
(6) Ability to coordinate aspects of development across multiple teams and multiple projects;
(7) Ability to troubleshoot hardware related problems;
(8) Ability and energy to make decisions under pressure.
3． Preferences:
(1) Wireless communication background;
(2) M.S. and higher degree.

职位名称：周边功能模块ASIC设计工程师
1．职责
(1) 评估不同供应商提供的周边功能模块的性能和价格；
(2) 验证这些功能模块；
(3) 在UWB片上系统(SoC)上集成功能模块；
(4) 通过顶层测试平台仿真验证功能模块。
2．资格
(1) 具有外围功能模块（PCI，USB和SDIO）集成、验证和排错的直接工作经验；
(2) 具有ASIC设计流程的丰富经验。
3．优先考虑:
具有FPGA经验者；硕士或以上学位。

Position title: Peripheral_ASIC Engineer
1． Responsibilities:
(1) Evaluation of peripheral IPs from different vendors in quality and price;
(2) Verification of these design Ips;
(3) Integration of IPs to the UWB SoC;
(4) Verification of IPs in the top level test bench simulation.
2． Qualification:
(1) Hands on experience on peripheral integration, verification and debugging of IPs such as PCI, USB and SDIO;.
(2) Solid experience on ASIC flow.
3． Priority:
(1) FPGA experience;
(2) MS and higher.

职位名称：资深ASIC验证工程师
Position title: Senior ASIC Verification Engineer
1． Responsibilities:
1) Working within an ASIC design team to develop reusable block-level and ASIC testbenches using high-level verification language (System Verilog).
2) Develop new ASIC verification environments to support ASIC development.
3) Review RTL architectural and implementation specifications.
4) Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC ASICs.
5) Define and implement code/functional coverage plans.
6) Develop testing and regression methodologies for new verification flow.
7) Incorporate reusability into all aspects of the verification environment.
8) Develop/maintain/enhance environment tools/scripts/makefiles.
2． Qualification:
1) Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design verification skills
2) Experience in using event-driven simulators like VCS
3) Fluent in Verilog for design verification
4) Experience in writing testbench using System Verilog
5) Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6) Knowledge of AMBA/AHB/DMA
7) Experience with one or more scripting languages: Perl, TCL, Shell
8) Superior debugging skills for large ASIC designs
9) Strong written and verbal communication skills
3． Required Degree:
MS Preferred Major: Electrical Engineering or related discipline

职位名称：资深数字后端设计工程师
Position title: Senior Digital Back-end Design Engineer
1. Responsibilities:
1) Responsible for developing and verifying complex digital designs with emphasis on backend tasks, including Floorplan, power planning and routing, CTS, PnR, RC extraction, ECO, DRC, LVS.
2) Work with RTL designers to optimize timing/area/power of the physical design implementation and perform static timing analysis.
2. Qualification:
1) 3-5 years experience in backend design flow with proven SOC tapeout experience.
2) Expertise in floorplan, place and routing, signal integrity, power analysis, CTS, DFT, ECO, DRC, LVS.
3) Experienced in Synopsys/Cadence) physical design tools and flows.
4) Experienced in Mentor’s Calibre flow for DRC/ERC/LVS/Antenna flow.
5) Strong timing analysis capabilities.
6) Experience with one or more scripting languages (Perl, TCL, Shell) to automate physical design flow.
7) Good analytical and debugging skills.
8) Strong written and verbal communication skills.
3. Required Degree:
BS Preferred Degree: MS Preferred Major: Electrical Engineering or related discipline

职位名称：资深高速数字滤波器设计工程师
Position title: Senior High Speed Digital Filter Design Engineer

1． Responsibilities:
(1) Develop high speed digital filter with custom design flow
(2) Low power optimization using custom design
2． Qualification:
(1) Solid experience in full custom high speed digital design development;
(2) Proficient in digital filter design
(3) Thorough understanding of CMOS device
3． Priority:
(1) High speed digital filter design
(2) CMOS full custom design flow
(3) Low power optimization with CMOS device

职位名称：资深MAC ASIC工程师
Position title: Senior MAC ASIC Engineer
1． Responsibilities:
(1) Develop MAC functional blocks for UWB SoC, including MAC datapath
(2) Perform verilog coding
(3) Support synthesis and timing closure
(4) Support FPGA based verification
2． Qualification:
(1) Solid experience in SoC development;
(2) Proficient in verilog coding;
(3) Thorough understanding of MAC;
(4) Solid experience in ASIC front end flow
(5) ARQ experience
(6) ARM/MIPS integration experience
3． Priority:
MAC implementation in ASIC, including ARQ implementation SoC development ASIC front end design and verification FPGA mapping and verification

感兴趣的可将简历发至ffxg@hotmail.com, 注明申请职位

PS：由于这些职位都是急招，所以希望能马上工作，因此将于2009年毕业的应届毕业生暂时不考虑

[ 本帖最后由 loisfun 于 2008-10-29 23:04 编辑 ]

作者: 21master 时间: 2008-10-29 14:18
xiexie

作者: wanghao831218 时间: 2008-10-29 21:49
标题: 应届硕士要不要？
应届硕士要不要？

作者: loisfun 时间: 2008-10-29 23:03
即将于09年毕业的应届毕业生暂时不考虑，sorry

作者: wxxuzhong 时间: 2008-10-30 20:09
提示: 作者被禁止或删除内容自动屏蔽

作者: zhanweisu27 时间: 2008-10-30 20:59
似乎贵公司玩的很高端

我喜欢，哈哈

不过不知对OFDM领域诸多专利怎么处理？

作者: ssdd_yy 时间: 2008-11-1 16:48
看看！！！！觉得还行

作者: milo_li 时间: 2008-11-1 23:08
好像一直挂着啊！！！！！！！！

作者: qhjqhjqq 时间: 2008-11-2 02:53
没说多少钱

作者: xhseu 时间: 2008-11-2 22:51

作者: ahaha111 时间: 2008-11-4 09:35
标题: 2222222222
22222222222222222

作者: ksj116 时间: 2008-11-4 14:44
标题: LZ又在忽悠大家了？
上海恒原是一家今年刚成立的公司，具体情况详见www.panovel.com ？？？？一看这个网址从事模拟IC设计一年的都知道这家公司早就成立了，成立至少有2年了。不知道LZ是猎头还是真的内部员工? 若是猎头还有情可原，要是内部员工就对不住大家了哈：）

作者: miju515 时间: 2008-11-6 11:02

原帖由 ksj116 于 2008-11-4 14:44 发表

 登录/注册后可看大图

上海恒原是一家今年刚成立的公司，具体情况详见www.panovel.com ？？？？一看这个网址从事模拟IC设计一年的都知道这家公司早就成立了，成立至少有2年了。不知道LZ是猎头还是真的内部员工? 若是猎头还有情可原， ...

难道是骗人的？或者传说中的骗简历？

作者: kingbeful 时间: 2008-11-6 21:46
对阿，直接点，多少米？

作者: ysg9999 时间: 2008-11-7 14:01
问下，今年毕业的硕士研究生，工作四个月的，要不要?

作者: piao 时间: 2009-1-22 23:28
公司现在还在吗？

作者: zhengdan66 时间: 2009-3-26 11:28

作者: EDALORD 时间: 2010-7-30 18:24
look at:
http://bbs.eetop.cn/thread-262624-1-1.html

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