知名EDA公司招聘后端设计工程师/ 前端设计工程师 / 前端验证工程师 base上海 / 北京

leviathanist

简历请投递至 3114835608@qq.com
以下岗位有效期一个月 招到即关


Title: Principal / Physical Design Engineer (数字后端设计Research方向)
Location: SH   


            Position Description:
•        Co-work with the R&D RTL design team for IP architecture exploration and optimization of the design and constraint
•        Co-work with other functional teams (Design/STA/Analog/Package/Verification) to optimize the high speed PHY IP development flow and set proper signoff criteria.
•        Optimize the physical implementation methodology and flow to meet the tight timing/power target of next generation high speed PHY IP.
•        Set and optimize the high speed PHY IP physical implementation guide which will be used by customers and internal global physical implementation teams.   
•        Perform physical design implementation tasks including floor planning, place & route, clock tree synthesis and Timing/PV/Power/Signal-EM/CLP/DFM signoff checks for some critical milestone projects.

            Position Requirements:      
•        BS degree with 5~10+ years of applicable experience, MS degree with 4~8+ years of applicable experience in electrical engineering, microelectronics.
•        Experienced with asic design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
•        Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
•        Successful track records of taping out complex, 16nm/10nm/7nm chips.
•        Automation and programming-minded, solid coding experience in Makefile /Tcl/Tk/Perl.
•        Innovative, self-motivated, able to work independently or as a team player.
•        Excellent verbal and written communication skills in English.

Title: Lead Physical Design Engineer (数字后端设计项目方向)
Location: SH / BJ

            Position Description:
•        Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
•        The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

            Position Requirements:      
•        BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
•        Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
•        Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
•        Successful track records of taping out complex, 16nm/10nm/7nm chips. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
•        Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.


Title: Principal / Lead Verification Engineer (数字前端验证)
Location: SH / BJ

           Position Description:
Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading  team projects and initiatives. Exercise judgment within generally defined practices and policies.
•        Specific duties include:
•        Deep understanding on ASIC design and verification flow
•        Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM
•        Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
•        Proficiency in System verilog, System C and/or e (Specman)
•        Developing and using Verification Components (eVC, OVC,UVC,VIP)
•        Developing and using assertion based verification and formal analysis methods
•        Skilled in scripting language, such as Perl, C shell, Python, Makefile
•        Assessing the project verification requirements

           Position Requirements:
           Essential Qualifications:
•        BS degree with 3+ years of applicable experience, MS degree with1+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
•        Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

           Desirable Qualifications:
•        Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
•        Will have demonstrated successful completion of 3+ verification projects as an individual contributor
•        Will have DDR project verification experience


Principal / Lead Front-end Design Engineer (RTL) （数字前端设计）
Location: SH / BJ

            Position Description:
•        Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
   
            Specific duties include:
•        Proficiency in logic design, simulation
•        Proficiency in Verilog and its simulation environment
•        Good knowledge of IC design
•        At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

            Position Requirements:
•        Essential Qualifications: Must have BS degree with 9~12+ years of applicable experience, MS degree with 7~10+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
•        Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
•        Will have demonstrated successful completion of 10+ design projects as an individual contributor
•        Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience


Title: Senior Principal Physical Design Engineer (数字后端设计项目方向)   
Location: SH

            Position Description:
•        Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
•        The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

            Position Requirements:      
•        BS degree with 15+ years of applicable experience, MS degree with 12+ years of applicable experience in electrical engineering, microelectronics.
•        Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
•        Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
•        Successful track records of taping out complex, 16nm/10nm/7nm chips. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
•        Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.

leviathanist

Add

Principle/Lead Product Engineer (SH/BJ) - Front-end SoC Verification

Requirements:
3~5years' experience in IC design house/EDA company
Experience in Verilog/VHDL, System Verilog/HDL simulators

简历请投递至 3114835608@qq.com

leviathanist

顶一下

leviathanist

Still open, urgent

gneisenau

CNDS？

leviathanist

回复 5# gneisenau


    Yes

leviathanist

Upon positions still open!!

Effective date due to August 31,2018.
Please kindly send both Chinese and English CV to 3114835608@qq.com
For any question, wechat vyu1104, thanks.


Add 2 more positions

Title: Principal Application Engineer (Physical Design Service)
Location: Shanghai

Position Description:
1.To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, for challenging low power designs, for 200MHz to several GHz big chips.
3.Have real design experience including conformal check, logic synthesis, P&R, CTS, SSTA, MMMC to close timing, power and die area.
4.Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
5.To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:
1.A bachelor's degree is essential and 6+ years’ experience in IC design, electronic engineering or computer science applications.
2.Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3.Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4.MS degree and/or working experience in multi-nation IC design house is a plus.

Title: Lead Application Engineer (Digital Backend)
Location: Shenzhen

Position Description:
1.To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs.
3.Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis.
4.Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
5.To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:
1.A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.
2.Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3.Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4.An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus.
5.Good communication in English and good work attitude.
6.Be familiar with shell/Perl/Tcl etc. script language.

leviathanist

Still open