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[招聘] Cadence 上海/北京急招大量数字前端/后端职位---2018年5月最新职位

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发表于 2018-5-27 22:08:34 | 显示全部楼层 |阅读模式

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Cadence 上海/北京急招大量数字前端/后端职位, 有意者请将简历发至541515639@qq.com, 在邮件标题中请注明应聘职位,谢谢!

Principal Front-end DesignEngineer (RTL)
(数字前端设计)

Location: BJ


           Position Description:

Ø
Deliver/implementDDR/HBM IP. The engineer should be able to act as a strong team member andcontributor. Exercise judgment within generally defined practices and policies.


           Specific duties include:

Ø
Proficiency inlogic design, simulation

Ø
Proficiency inverilog and its simulation environment

Ø
Good knowledge ofIC design

Ø
At least sevenyear experience working on digital IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.


            Position Requirements:

Ø
EssentialQualifications: Must have BS degree with 9~12+ years of applicable experience,MS degree with 7~10+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

Ø
Essential that theindividual demonstrates strong communication, verbal and written.

Requires good communication skills in English.

Ø
Will havedemonstrated successful completion of 10+ design projects as an individualcontributor

Ø
Familiar withJEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience

Titlerincipal Physical Design Engineer (数字后端设计Methodology方向)

Location:SH      

·

Position Description:

Ø
Co-work with theR&D RTL design team for IP architecture exploration and optimization of thedesign and constraint

Ø
Co-work with otherfunctional teams (Design/STA/Analog/Package/Verification) to optimize the highspeed PHY IP development flow and set proper signoff criteria.

Ø
Optimize thephysical implementation methodology and flow to meet the tight timing/powertarget of next generation high speed PHY IP.

Ø
Set and optimizethe high speed PHY IP physical implementation guide which will be used bycustomers and internal global physical implementation teams.   

Ø
Perform physicaldesign implementation tasks including floor planning, place&route, clocktree synthesis and Timing/PV/Power/Signal-EM/CLP/DFM signoff checks for somecritical milestone projects.



Position Requirements:      

Ø
BS degree with5~10+ years of applicable experience, MS degree with 4~8+ years of applicableexperience in electrical engineering, microelectronics.

Ø
Experienced withasic design flow, hierarchical physical design strategies, and methodologiesand understand deep sub-micron technology issues.

Ø
Solid knowledge onLP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physicalverification, DFM.

Ø
Successful trackrecords of taping out complex, 16nm/10nm/7nm chips.

Ø
Automation andprogramming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

Ø
Innovative,self-motivated, able to work independently or as a team player.

Ø
Excellent verbaland written communication skills in English.

Title: Senior Principal Physical Design Engineer(数字后端设计项目方向)  

Location: SH

           Position Description:

Ø
Performphysical design implementation, including floor planning, power grid design,place and route, clock tree synthesis, timing closure, power/signal integritysignoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Ø
Thecandidate will have the opportunity to work on many varieties of challengingdesigns, i.e. low power and high speed design. The responsibility includesparticipating in or leading next generation PHY IP physical design, methodologyand flow development.


           PositionRequirements:        

Ø
BSdegree with 15+ years of applicable experience, MS degree with 12+ years ofapplicable experience in electrical engineering, microelectronics.

Ø
Experiencedwith ASIC design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues.

Ø
Solidknowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis,physical verification, DFM.

Ø
Successfultrack records of taping out complex, 16nm/10nm/7nm chips. Automation andprogramming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

Ø
Self-motivated,able to work independently or as a team player, excellent verbal and writtencommunication skills in English.

Title: Lead Physical Design Engineer (数字后端设计项目方向)

Location: BJ

           Position Description:

Ø
Performphysical design implementation, including floor planning, power grid design,place and route, clock tree synthesis, timing closure, power/signal integritysignoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Ø
Thecandidate will have the opportunity to work on many varieties of challengingdesigns, i.e. low power and high speed design. The responsibility includesparticipating in or leading next generation PHY IP physical design, methodologyand flow development.


           PositionRequirements:        

Ø
BSdegree with 5+ years of applicable experience, MS degree with 3+ years ofapplicable experience in electrical engineering, microelectronics.

Ø
Experiencedwith ASIC design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues.

Ø
Solidknowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis,physical verification, DFM.

Ø
Successfultrack records of taping out complex, 16nm/10nm/7nm chips. Automation andprogramming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

Ø
Self-motivated,able to work independently or as a team player, excellent verbal and writtencommunication skills in English.

Title: Principal / Lead Verification Engineer (数字前端验证)

Location: SH

          PositionDescription:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading  team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Ø
Specificduties include:

Ø
Deepunderstanding on ASIC design and verification flow

Ø
Excellentknowledge of advanced verification methodology like eRM/OVM/UVM/VMM

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Familiarwith Cadence’s Incisive Plan to Closure Methodology (IPCM)

Ø
Proficiencyin System Verilog, System C and/or e (Specman)

Ø
Developingand using Verification Components (eVC,OVC,UVC,VIP)

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Developingand using assertion based verification and formal analysis methods

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Skilledin scripting language, such as Perl,C shell,Python,Makefile

Ø
Assessingthe project verification requirements

          Position Requirements:

          Essential Qualifications:

Ø
BSdegree with 3+ years of applicable experience, MS degree with1+ years ofapplicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics.

Ø
Essentialthat the individual demonstrates strong communication, verbal and written.Requires good communication skills in English.


         Desirable Qualifications:

Ø
Willhave demonstrated hands-on experience and expertise with Cadence verificationdesign tools or equivalent tools, flows and methodologies required to execute averification project.

Ø
Willhave demonstrated successful completion of 3+ verification projects as anindividual contributor

Ø
Willhave DDR project verification experience


 楼主| 发表于 2018-5-31 14:18:33 | 显示全部楼层
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 楼主| 发表于 2018-6-8 15:38:59 | 显示全部楼层
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 楼主| 发表于 2018-6-12 17:40:18 | 显示全部楼层
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 楼主| 发表于 2018-6-15 16:32:54 | 显示全部楼层
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 楼主| 发表于 2018-6-27 12:07:43 | 显示全部楼层
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