module four
(
output reg [7:0] led,
input I_sys_clk
);
reg [7:0] led_stage;
reg [50:0] led_counter;
always@(posedge I_sys_clk )
begin
case(led_stage)
8'b00000000:
begin
led_counter<=0;
led_stage<=8'b00000001;
led<=8'b11110000;
end
8'b00000001:
begin
if(led_counter==30000000)
begin
led<=~led;
led_counter<=0;
end
else
begin
led_counter<=led_counter+1;
end
end