IC设计公司招聘 集成电路后端设计工程师/Physical Design Engineer

AvailinkHR

意向沟通/申请岗位，请发送简历至elaine.wang@availink.com，收到简历我们将即刻与您联系。谢谢。

CompanyIntroduction:     Availink Inc. is atechnology-driven fabless semiconductor company, focusing on the multimedia anddigital TV industries.  Availink Inc. isbacked by premiere financial institutions, with offices in China and the United States and with targetedconsumer markets around the world. By grouping a great team of professionals,building multiple product lines in fast growing markets, and attractingfirst-tier customers, Availink is positioned to grow into a significant playerin the field.   If you are a hands-on,results-oriented and energetic individual, and like to take this opportunity togrow and strive to achieve the best results, Availink will offer you achallenging and rewarding career.

Position Tasks, Duties andResponsibilities

The asic Physical Design Engineerwill:

•
Performfull synthesis (RTL synthesis, place & route) of standard cell IC.

•
Performlibrary, IP, and IC design service evaluation and selection.

•
Completethird party IP integration and ensure vendor guidelines are followed.

•
Workwith front-end engineers to resolve problems and achieve design closure.

•
Adhereto established design methodology and contribute to its continuous improvement

•
Usescripting languages, configuration management, batch processing, and othertechniques to ensure design quality and minimize turnaround time

•
Maintainlinux sever and EDA tools.

Candidate Qualifications:

Candidate must:

•
HoldBSEE (MS preferred).

•
Haveminimum of 5 years hands-on experience in full flow IC back-end physical designand verification

•
Havecompleted hierarchical IC projects experience in 40nm and below.

•
Havethe ability to independently identify and resolve design, tool, and flowproblems

•
Beable to design and implement physical design strategies and methodologies fordeep submicron designs.

•
Beable to complete block and chip level tapeout quality LVS and DRC

•
Familiar with Linux environments, familiar with EDAtool.

Any of the following is beneficial:

•
STAconstraint design

•
Equivalencechecking – RTL to gates, and gates to gates

Tasks include all aspects of thephysical design flow such as:

•
RTL synthesis

•
IC physical design flow

•
Floorplanning and powergrid implementations

•
Hierarchical design partitioning

•
Placement of standard cells

•
Scan insertion / scan chainreordering

•
Analog IP integration

•
Power and IR drop analysis

•
Clock tree synthesis

•
Routing

•
Parasitic extraction

•
Timing verification

•
Timing improvements forcritical macro blocks

•
Timing closure

•
Noise analysis

•
DFM analysis andimprovement

•
Signoff LVS/DRC

•
Implementation of posttapeout ECO changes