详细JD如下:
Digital Verification Engineer
Responsibilities:
1. Creating test plan according to design spec
2. Designing and developing verification environment;
3. Debugging SoC regression failure
4. Creating system checker/monitors and system UVCs, code & function coverage in SOC
5. Creating C test case running on arm in SOC
6. Creating UVM test case in SOC
Qualifications:
1. Education and Experience-Bachelor or above with 3 years of work experience
2. Skills and Knowledge- verilog
System Verilog
UVM
Perl/Python/Tcl
AXI/AHB/APB
Co-sim between hardware and software is an additional plus
C/C++ is an additional plus
USB/Ethernet/PCIE/SATA/SPI/I2C/etc. experience is an additional plus
ARM related experience is an additional plus