Verilog Logic Designer

jackapple · 发表于 2017-7-2 10:20:06

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本帖最后由 jackapple 于 2017-7-11 05:54 编辑

Job Opening for the verilog logic designer
Location: China
Job description:
1. Verilog/System Verilog logic design/verification

Job requirements:
1. DDR3/4/LPDDR3/4 logic design/verification experience
2. Synopsys/Cadence DDR controller experience
3. Synopsys/Cadence VIP experience
4. Nice to have UVM experience

High paid, please help to send your resume to ddrlpddr@163.com

chineselboy · 发表于 2017-7-2 12:47:55

回复 1# jackapple

How to contact with you？

jackapple · 发表于 2017-7-3 20:36:36

Please send your resume to ddrlpddr@163.com

chineselboy · 发表于 2017-7-5 12:07:54

回复 3# jackapple

I can send you the message here. Can you send me a message with your weichat ID, please? Thanks

jackapple · 发表于 2017-7-8 13:46:57

Please help to send your resume to ddrlpddr@163.com

zrzf23 · 发表于 2017-8-5 21:21:36

work where ?

[招聘] Verilog Logic Designer

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