|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
I don't have much Vhdl coding experience, please help for the follow code
IO1 port is defined in component section
port(
...
...
IO1 : inout std_logic_vector(31 downto 0);
...
);
at the time of calling this module, we have both RegPort_B and RegPort_C defined as output and input
respectively:
RegPort_B : OUT std_logic_vector ( 15 DOWNTO 0);
RegPort_C : IN std_logic_vector (15 DOWNTO 0);
so IO1 as output I coded: in port map section
IO1 => noCon(15 downto 0) & RegPort_A(15 downto 0),
for an instance
and as input:
IO1 => B"0000000000000000" & RegPort_C(15 downto 0),
for another instance
but I got errors for both:
55: IO1 => B"0000000000000000" & RegPort_C(15 downto 0),
^
[Error] Actual must be a signal or port (or a type conversion on a signal or port)
and
79: IO1 => noCon(31 downto 16) & RegPort_B(15 downto 0)
^^^^^^^^^
[Error] Read error: trying to read port of mode OUT
please help |
|