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简历请投递:job_china@cadence.com(简历投递格式:姓名+申请职位+工作地点)
工作地点:上海市浦东新区芳甸路1155号浦东嘉里
R&D( Product Solution Engineer)
1. PrincipalSolutions Engineer- Protium FPGA
PositionDescription: The ProtiumPrincipal Solutions Engineer position is responsible for both creating anddeployment new technology and solutions for Cadence Protium FPGA PrototypingPlatform. The job function involves the following: 1. Support customersand field to map asic designs to Protium FPGA prototyping platform 2. Create newsolutions for Protium FPGA prototyping platform that involve creating RTLdesigns for FPGA, board designs for accessories or developing advancedprototyping flows and methodologies 3. Working withR&D to define and review future product capabilities 4. Manage betaprograms and launch of new products 5. Prepare Cadencefield resources for new deployments including AE training and collateraldevelopment like application notes, reference designs, demos 6. Assist field andcustomers on root causing complex issues on Protium FPGA prototyping platform
Position Requirements:
1. The positionrequires BSEE, or equivalent, with a minimum of 5 years of industry experiencewith FPGA based hardware solutions. Must have excellent communication skillswith both written and spoken English.
2. Deep technicalexpertise in FPGA design for either Altera or Xilinx products is required.Expert knowledge in FPGA design methodologies including high speed design,serial protocols and FPGA timing closure is also required. 3. Must haveexcellent hardware and system debug capabilities. 4. RTL designknowledge using verilog/System Verilog is required along with experience usingRTL verification tools and flows. Verification experience using Cadencesimulation and/or emulation products is highly desired. Programming experiencewith scripting languages like Perl, TCL, C-shell is strongly recommended.
2. Sr Principal Solutions Engineer, HSV PE
Location:SH/SZ Position Description: He/shewill lead and be a participating member of a team of advanced field engineerswho deploy and support advanced hardware based verification flow integrationtechnical engagements and provide easy-to-adopt packages and workshops toCadence field application engineers and customers alike. He/shewill focus on the technical aspects of the following hardware verificationsolutions for customer engagements as well as creating demos/workshops to trainfield AE and customers: (1)Cadence Palladium HW Acceleration Platforms (2)Cadence Acceleratable Verification IP portfolio (3)HSV product integration with other Cadence products such as Incisive Simulationand/or Joules for power analysis (4)HW/SW Co-verification solutions for SoC designs Theperson must be a strong team leader and contributor, leading projects andinitiatives for the local regions and maintain a strong connection with the USteam. He/She must be able to travel and coach AEs among AP regions for multipleengagements. HWbased verification experience such as other emulators or FPGA prototyping basedverification is required Expertisein RTL top-down design and verification methodology automation are required.This includes full hands on knowledge of writing and debugging Verilog, Vhdland SystemVerilog based D&V environments. Wewould also like the candidate to have good knowledge of SoC design principles,embedded software development and HW/SW co-design and co-verification. Theperson should possess team-success orientation, mature work attitude, and goodjudgment under pressure. Position Requirements:
1. Minimum Education Required: education level of BS with 12+ years’ experience(or MS with 10+ or more years’ experience).
2. A good knowledge of RTL design and verification tools (HDLs, synthesis tools,design simulation, acceleration using emulators). 3. Knowledge of the needs of SoC design and verification. 4. Knowledge of UNIX, C/C++, other scripting programming languages (Perl, TCL…) ishighly desired. 5. Strong verbal and written communication skills in English are required. 6. At least 12+ years’ experience in the following areas: -HW acceleration or In-Circuit Emulation or FPGA prototyping experience is amust -Hardware verification, including knowledge of HDL simulators and debuggingsimulations -Hands on experience with using design and verification languages like SystemC,SystemVerilog (IEEE 1800) and VHDL is a must. -Knowledge of embedded systems and software development for SoCs is a plus
R&D(Design Engineer)
1. Lead DesignEngineer--Memory Modeling Portfolio
Position Description:
1. Responsible for scheduling, designing, developing, andsupporting IP models of system level memory such as SDRAM (LPDDR, HBM), NANDFlash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardwarebased verification products.
2. Rsponsible for updating, maintaining,documenting, and supporting existing system level memory model products. 3. Perform as individual contributor for RTL design, verification, productizing,and documentation of memory IP. 4. Interface with internal and external customersto work on diverse problems and solutions related to emulation, simulation, orverification. 5. Perform as team member toward cross verification of and crosstraining in memory IP as well as in developing and using lifecycle processes toensure product quality. Position Requirements:
1. The position requires BSEE, or equivalent, with a minimumof 4 years of industry experience in designing hardware systems.
2. Must haveexcellent communication skills with both written and spoken English. 3. RTL designknowledge using Verilog/System Verilog is required along with experience usingRTL verification tools and flows. 4. Debugging experience. Experience withteam-wide collaboration tools and process. 5.Drive and ability to scheduleworkload and plan own tasks effectively. 6. Strongly recommended: Verification experience usingCadence simulation and/or emulation products is highly desired. Programmingexperience with scripting languages like Perl, TCL, C-shell is stronglyrecommended. Experience in memory sub-system design and operation is stronglyrecommended.
R&D(Software Engineer)
1. Lead Software Engineer (Emulationsoftware)
PositionDescription: 1. We are looking fora Lead Software Engineer to work in a team oriented environment to develop andmaintain advanced emulation and co-simulation run-time software tools andtransaction-based acceleration (TBA) methodology. 2. The engineer will workclosely with application engineers to develop high performance TBA solutionsusing TBA technologies on Cadence emulation/prototyping platforms.
3. Responsibilitiesinclude development of software tools for Palladium emulation system, emulationand co-simulation run time commands and various core run time software modulesfor existing and future generation emulation systems.
4. Responsibilities includedevelopment of TBA solution kits and performance tuning on deployment.
PositionRequirements:
1. This positionrequires a Bachelor or Master Degree in EE/CS/CE with 3-5 years of industryexperience. 2. Candidate shouldbe proficient with C/C++, Operating system concepts. 3. Design modelingusing Verilog/SV, VHDL or SysC. 4. Knowledge andexperience in RTL modeling of BFMs along with exposure to verificationmethodologies using UVM and SC/TLM is preferable. 5. EDA/CAD tooldevelopment experience or logic design verification experience is highlypreferred. 6. Requires goodcommunication skills, attention to details, and ability to work inmulti-site/multi-person project.
2. Lead Software Engineer- LogicSynthesis
Position Description:
1. Responsible fordevelopment and maintenance of the synthesizer for Palladium.
2. Implementation fornew VHDL/Verilog feature support in synthesizer.
3. Logic optimizationand performance improvement in synthesizer.
PositionRequirements:
1. MS above in CS/EE or similar level ofexpertise with 3+ years of working experience.
2. Be skilled inC/C++ programming on Linux platform. 3. Good team playerwith strong written and verbal communication skills. 4. Familiar with VHDL/Verilogand knowledge on EDA tools of simulation, synthesis is required. 5. Familiar with thedistributed computing and database development is preferred.
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