verilog条件生成和条件编译的区别

xduryan

`ifdef `else `endif和generate...if...endgenerate之间的区别与联系，是否能相互替换？

知道的大神讲讲呗

neoitachi

`ifdef, `else, `elsif, `endif, `ifndef:These conditional compilation compiler directives are used to include optionally lines of a Verilog HDL
source description during compilation. The `ifdef compiler directive checks for the definition of a
text_macro_name. If the text_macro_name is defined, then the lines following the `ifdef directive
are included. If the text_macro_name is not defined and an `else directive exists, then this source is
compiled. The `ifndef compiler directive checks for the definition of a text_macro_name. If the
text_macro_name is not defined, then the lines following the `ifndef directive are included. If the
text_macro_name is defined and an `else directive exists, then this source is compiled.
If the `elsif directive exists (instead of the `else) the compiler checks for the definition of the
text_macro_name. If the name exists the lines following the `elsif directive are included. The `elsif
directive is equivalent to the compiler directive sequence `else `ifdef ... `endif. This directive does not need a
corresponding `endif directive. This directive must be preceded by an `ifdef or `ifndef directive.
These directives may appear anywhere in the source description.


generate..if...endgenerate
Generate statements allow control over the declaration of variables, functions and tasks, as well as control
over instantiations. Generated instantiations are one or more: modules, user defined primitives, Verilog gate
primitives, continuous assignments, initial blocks and always blocks. Generated declarations and instantiations
can be conditionally instantiated into a design. Generated variable declarations and instantiations can
be multiply instantiated into a design.

不清楚的地方可以仔细看一下LRM，第一种属于预编译命令，发生在parse阶段。第二种属于生成语句，发生在elaboration阶段。