在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
查看: 2085|回复: 1

[招聘] 【招聘】AMD内推后端PR(Physical Design)

[复制链接]
发表于 2015-11-26 22:44:22 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
我老板招人,需要后端经验。

有兴趣请投递简历至:
286404234@qq.com
我会先跟您初步了解一下。

Job Description:
Physical design of deep sub-micron chips including block level floorplanning, place&route, cts, routing, physical verification, sta, si closure , power closure.

Qualification:
1. Master and above of EE.
2. Experience on place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, sta.
3. Knowledgeable in all aspects of deep submicron asic design flow.
4. Familiar with Back-End (physical design) EDA tools.
5. Familiar with Front-End EDA tools or circuit design is a plus.
6. Familiar with Unix/Linux environment and good at scripts (tcl/perl).
7. Strong passion in achievement and career development.
8. Good English listening, writing and speaking ability.
9. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player.
发表于 2015-11-30 18:13:33 | 显示全部楼层
回复 1# magictracyguy


   支持一下
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /3 下一条

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-4-19 09:30 , Processed in 0.021739 second(s), 8 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表