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发表于 2017-7-21 17:09:52
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基于以上原理,VIVADO2017.2也是可以解出的:
------------------------------------------------------------------------
-- Filename : can_top.vhd
-- Version : 1.00.a
-- Author :
-- Company : Xilinx
-- Description : Top level design, instantiates IPIF and top module for CAN core.
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- can_top.vhd
-- -- cantop.vhd
-- -- can_tl_top.vhd
-- -- can_tl_synch.vhd
-- -- can_tl_clkdiv.vhd
-- -- can_tl_om.vhd
-- -- can_tl_bsp.vhd
-- -- can_tl_arbit.vhd
-- -- can_tl_btl.vhd
-- -- can_tl_acf.vhd
-- -- can_ol_top.vhd
-- -- can_txfifo_cntl_gen.vhd
-- -- can_ol_fifopriority.vhd
-- -- can_tl_arbchk.vhd
-- -- can_rxfifo_cntl_gen.vhd
-- -- can_ol_synch.vhd
-- -- can_ic_main.vhd
-- -- can_bram.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library can_v5_0_16;
use can_v5_0_16.proc_common_pkg.all;
use can_v5_0_16.ipif_pkg.all;
--------------------------------------------------------------------------------
-- Entity section
--------------------------------------------------------------------------------
entity can_top is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_CAN_RX_DPTH : integer := 64;
C_CAN_TX_DPTH : integer := 64;
C_CAN_NUM_ACF : integer := 4;
C_S2C_MTBF_STAGES : integer := 2; -- Number of MTBF Stages for System to
-- CAN CLK Crossing.
C_C2S_MTBF_STAGES : integer := 2; -- Number of MTBF Stages for CAN to
-- System CLK Crossing.
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- axi lite ipif block generics
C_S_AXI_ADDR_WIDTH : integer := 8;
C_S_AXI_DATA_WIDTH : integer := 32;
C_FAMILY : string := "virtex7"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CAN_CLK : in std_logic;
CAN_PHY_RX : in std_logic;
CAN_PHY_TX : out std_logic;
IP2Bus_IntrEvent : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- AXI interface signals
S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute SIGIS of IP2Bus_IntrEvent : signal is "INTR_EDGE_RISING";
--------------------------------------------------------------------------
-- IP licensing section
--------------------------------------------------------------------------
attribute check_license : string; |
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