Cadence 166 Hotfix 039

suiwinder · 发表于 2014-11-16 14:25:14

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本帖最后由 suiwinder 于 2014-11-19 20:19 编辑

DATE: 11-14-2014 HOTFIX VERSION: 039
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1213239 FLOWS       PROJMGR       SPI_ERROR: Missing closing quote at line 41 in""
1301262 SPIF          OTHER          When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.
1301469 CONCEPT_hdl CORE          DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default
1309535 SYSTEMSI    ENG_PBA       PA5700: Cannot print, save, or post process SI analysis reports
1317019 SIG_INTEGRITY  LIBRARY       Buffer model for pins not changing correctly when multiple DML files are present in working directory.
1318452 ALLEGRO_EDITOR DATABASE       Derive Connectivity does not update connections; DRC errors thrown
1318610 CONCEPT_HDL CORE          DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager
1320997 CAPTURE       SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.
1321377 FSP          GUI             FSP crashes while performing copy-paste operations between different arrays in the Rule text editor
1321513 ALLEGRO_EDITOR SYMBOL          Preview not available for DRA
1324479 ALLEGRO_EDITOR OTHER          Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX
1327962 FSP          MODEL_EDITOR    Need ability to select multiple pins in the Preview area of Rule Editor
1328633 CONCEPT_HDL CORE          On running Save All, changes were partially saved before DE-HDL crashed.
1328921 ALLEGRO_EDITOR DATABASE       Running Derive Connectivity followed by Database Check throws SPMHUT-17 error
1330029 CONCEPT_HDL CORE          PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design
1330580 SIP_layout    SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated
1331028 CONCEPT_HDL CHECKPLUS       Rules Checker fails on DE-HDL component.
1331051 ALLEGRO_EDITOR INTERFACES    Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B
1333127 CONCEPT_HDL CORE          Sheet number in the new window is only the block-level number and not the design-level number
1333591 SIP_LAYOUT    SKILL          Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack
1333896 ASI_SI       OTHER          signoise -f and -k options don't work for net names with consecutive underscores.
1333982 ALLEGRO_EDITOR ARTWORK       ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.
1334302 CONSTRAINT_MGR SCHEM_FTB       Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
1335276 CONCEPT_HDL OTHER          On selecting objects near the schematic page border, the border is also selected
1336322 CONCEPT_HDL CORE          DE-HDL does not open with maximized window.
1336783 PCB_LIBRARIAN  IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format

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