An Evaluation of CoWare Processor Designer for the Design of Embedded Processors

ald_syn_cad · 发表于 2012-10-23 17:23:05

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本帖最后由 ald_syn_cad 于 2012-10-23 17:26 编辑

An Evaluation of CoWare Inc.’s Processor Designer Tool Suite for the Design of Embedded Processors
Jonathan D. Franz, M.S.E.C.E
Advisor: Russell W. Duren, Ph.D.

Abstract
The goal of this thesis is to evaluate the Processor Designer family of tools from CoWare, Inc. Processor Designer uses the L.I.S.A. 2.0 (Language for Instruction Set Architecture) language. The evaluation is being performed to determine the suitability of the toolset for incorporation into a classroom environment and for the use in developing replacements for legacy processors. The main focus will be on the ease of use of the tools. This includes exploring how steep of a learning curve is involved with this new processor designer language and how well the tools have been documented. The limitations of the tools will also be explored, as far as what can and cannot be done in the language. The thesis is also intended to provide a tutorial introduction to the CoWare Inc. tool suite for future students.
.................................
See also:
http://bbs.eetop.cn/viewthread.p ... rocessor%2BDesigner

tedazsx · 发表于 2012-10-23 18:39:18

没有软件，
如何能够 evaluate ？？

ald_syn_cad · 发表于 2012-10-23 20:09:52

It's the name of the thesis. It's the only guide that I could find for the Processor designer. The soft is on eetop also crack exists.

tedazsx · 发表于 2012-10-23 21:09:33

本帖最后由 tedazsx 于 2012-10-23 21:11 编辑

It's the name of the thesis. It's the only guide that I could find for the Processor designer. The s ...
ald_syn_cad 发表于 2012-10-23 20:09

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哦，想起来了。
是有一个，不过好像2009的好使，可是2010的那个pj不太好使——可以打开，但是一编译例子程序就报错，我折腾了好久也不管用。

此外，没有LISA，光有processor designer，是不是也没有太大用处啊？？

ald_syn_cad · 发表于 2012-10-23 22:31:19

Sorry my Chinese is not good enough but I am not a fan of processor designer because of hard efforts should be done and after that designing subsequent compilers for your application codes and testing the correct functionality is not an easy job. By the way nowadays CPU models are designed in SystemC for integrating them in the TLM flow for the SOC designs. I suggest to forget about processor designer and try to get access to e.g. http://www.ovpworld.org/ models (as you have uploaded). There are pre-verified models for the of the shelf models (like ARM, etc....) and can be used in the leading tools like Mentor vista, Synopsys Platform architect or cadence System Development Suite. Also these models can be semi customized that satisfy your need.
Using processor designer in my opinion is good for academic researches and for commercialized uses you should do a lot with it that I am not that kind of person.

xin_ming_wang · 发表于 2012-10-23 23:09:59

actually, i have uploaded some resources about coware/synopsys pd and pa, even spw.
but, nobody will share on internet the key of these softwares, namely, the cosy compiler of pd, the processor/interconnect ip of pa, and the license even the installer of spw.

probably, you have been keeping an eye on coware's 3 tools since a few years ago, but who really get it for free?

ESL tools are different from traditional IC design tools.
vendors of different ic design tools have got their stable market share by now .
but the field of ESL are under competition.

that is why synopsys keep swallowing other ESL vendors, and why so many "just-for-learning" other than the key resources appear on this bbs.
because these ESL vendors want their tools get accepted by as many people as possible, without the key of their tools shared for free on the internet.

ald_syn_cad · 发表于 2012-10-24 13:48:12

本帖最后由 ald_syn_cad 于 2012-10-24 13:50 编辑

actually, i have uploaded some resources about coware/synopsys pd and pa, even spw.
but, nobody wil ...
xin_ming_wang ??? 2012-10-23 23:09

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I totally agree with you. Read the below doc and feel the never ending pain and complexity. It's for 2008. I should admit that ESL world has peeled regularly and lots of times but still ESL is the most challenging part of hardware/software and aggregately most system designs and you'd be 100% drowned if you'll get stuck with it.

http://www.ovpworld.org/versions_ovp/20120614.5/download.php?f=f4d58aafa46008a659cf3ad5bf78def9.zip&fc=BrianBaileyWhitePaper_SLVP_and_OVP.pdf

AliceCooper · 发表于 2012-10-30 06:17:31

This is a GREAT RESEARCH THESIS:
THEY FOUND OUT THAT COWARE IS LESS EFFICIENT THAN HAND WRITTEN MODELS

xin_ming_wang · 发表于 2012-10-31 00:57:30

本帖最后由 xin_ming_wang 于 2012-10-31 12:50 编辑

well, for all EDA tools, we should realize that nearly all automatically generated codes are less efficient than their hand-written counterparts. the processors yielded by pd are only demos, and are far from mature.

according to my true story, i can tell you that, the key of processor designer is its ability to quickly prove or demo something. for example:
1) you can quickly prove your novel idea on a specific processor architecture, through the automatically generated software tool chain and rtl codes, without bitterly writing assembly program codes and rtl implementation. this means pd is more suitable for academic use in my opinion.
2) if a company/university or something else have designed (or want to design) their own processors, they will find they are stuck by the compiler and simulator even though open-source compilers like gcc from GNU are on their hands. because they know (actually, their are right) it is nearly impossible to port gcc for their architectures in so short time by so few people. it is always true for Chinese universities or institutes. thus, they need pd to quickly model their processors, and quickly provide the associated software tool chain, to quickly show someone (usually the gov) that they can do processor design on their own, and they can be assigned more challenging (thus more money) works.

ald_syn_cad · 发表于 2012-10-31 02:39:09

well, nearly all automatically generated codes are less efficient than their hand-written counterpar ...
xin_ming_wang 发表于 2012-10-31 00:57

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Thanks so much for the info!
I have the same opinion. If it was an easy task, companies would invest on ASIP not ASIC. Processor designing is one task and designing compilers are the other one. If you search on the internet you would find dozen of thousands of ASIC core providers and lots of even big SOC companies do not fund on their own processors and use major GPP (like ARM processor) providers (less efficient for specific tasks) like:
http://en.wikipedia.org/wiki/List_of_microprocessors

An Evaluation of CoWare Processor Designer for the Design of Embedded Processors

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