calibre lvs 报错

DruculaC · 发表于 2012-3-13 17:30:53

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报错如下:  像是加的port没有连接到metal1，在after transformation后，net变多了。改如何设置呢？

Extraction Errors and Warnings for cell "inv.calibre.db"
---------------------------------------------------------

WARNING:  Unattached label:
      Name  "VDD!"  at location  (1.08,1.735)  on layer  141

WARNING:  Unattached label:
      Name  "OUT"  at location  (4.67,6.53)  on layer  141

WARNING:  Unattached label:
      Name  "IN"  at location  (5.475,9.15)  on layer  141

WARNING:  Unattached label:
      Name  "GND!"  at location  (8.495,9.73)  on layer  141

WARNING:  Unattached port pads; port ignored:
      Port name:  VDD!  on layer  141  at location  (1.08,1.735)

WARNING:  Unattached port pads; port ignored:
      Port name:  OUT  on layer  141  at location  (4.67,6.53)

WARNING:  Unattached port pads; port ignored:
      Port name:  IN  on layer  141  at location  (5.475,9.15)

WARNING:  Unattached port pads; port ignored:
      Port name:  GND!  on layer  141  at location  (8.495,9.73)

WARNING: Invalid PATHCHK request "GROUND && ! POWER": no POWER nets present, operation aborted.

WARNING: Invalid PATHCHK request "POWER && ! GROUND": no POWER nets present, operation aborted.

WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no POWER nets present, operation aborted.

WARNING: Invalid PATHCHK request "! LABELED": no LABELED nets present, operation aborted.

               ##################################################
               ##                                           ##
               ##       C A L I B R E S Y S T E M       ##
               ##                                           ##
               ##          L V S R E P O R T             ##
               ##                                           ##
               ##################################################

REPORT FILE NAME:       inv.lvs.report
layout NAME:             inv.calibre.db
SOURCE NAME:             /home/tsm0001/verify/out_richard/inv.src.net ('inv')
RULE FILE:             /home/tsm0001/verify/out_richard/_SmicSP2T_cal035_epm_realhv3.3V_p2mtx.lvs_
LVS MODE:                Mask
RULE FILE NAME:          /home/tsm0001/verify/out_richard/_SmicSP2T_cal035_epm_realhv3.3V_p2mtx.lvs_
CREATION TIME:          Tue Mar 13 16:45:46 2012
CURRENT DIRECTORY:       /home/tsm0001/verify/out_richard
USER NAME:             tsm0001
CALIBRE VERSION:       v2011.2_34.26 Wed Jul 6 05:20:09 PDT 2011

**************************************************************************************************************
                           OVERALL COMPARISON RESULTS
**************************************************************************************************************

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of nets (see below).
  Error: Connectivity errors.

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             4       4

Nets:             4       4

Instances:       1       1       MN (4 pins)
                  1       1       MP (4 pins)
            ------ ------
Total Inst:       2       2

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             4       4

Nets:             8       4 *

Instances:       1       1       MN (4 pins)
                  1       1       MP (4 pins)
            ------ ------
Total Inst:       2       2

   * = Number of objects in layout different from number in source.

lvs文件中关于port的定义如下：

TEXT LAYER 141 ATTACH 141 metal1
PORT LAYER TEXT 141
TEXT LAYER 61 ATTACH 61 metal1
PORT LAYER TEXT 61
#IFDEF TOPMETAL 3
TEXT LAYER 143 ATTACH 143 metal3
PORT LAYER TEXT 143
TEXT LAYER 363 ATTACH 363 metal3
PORT LAYER TEXT 363
TEXT LAYER 142 ATTACH 142 metal2
PORT LAYER TEXT 142
TEXT LAYER 62 ATTACH 62 metal2
PORT LAYER TEXT 62
#ENDIF
#IFDEF TOPMETAL 2
TEXT LAYER 142 ATTACH 142 metal2
PORT LAYER TEXT 142
TEXT LAYER 62 ATTACH 62 metal2
PORT LAYER TEXT 62
#ENDIF

motofatfat · 发表于 2012-3-13 18:04:55

看起來有可能像是 m1_text 沒貼在 metal1 上的情形

xycxyc1989 · 发表于 2012-3-13 20:02:29

回复 1# DruculaC

那label没对应到相应的层上啊

terry8876 · 发表于 2012-3-13 22:09:37

你再看看电路，顶层电路是几个pin，是什么名字你就用几个pin及对应的名字，不要把底层的pin打到顶层来。
比如你的INV输入输出为IN,OUT，但在顶层接的A,B。你若用Label把IN,OUT,A,B都打到顶层cell了的话LVS可能会报错。

DruculaC · 发表于 2012-3-15 12:57:00

回复 4# terry8876

就一个反相器，没有调用层。另外你们说的label是指打pin的时候写的名字吗？

DruculaC · 发表于 2012-3-15 12:58:12

回复 2# motofatfat

我把M1TXT画在M1上，calibre应该是自动认定这个pin链接到了M1上才对呀。。

DruculaC · 发表于 2012-3-15 13:45:31

回复 3# xycxyc1989

应该怎么对应呢？

motofatfat · 发表于 2012-3-15 17:25:05

選用 M1_TEXT layer
Create Lable
讓 + 落在 metal1 上

half_honey · 发表于 2012-3-16 08:39:39

回复 6# DruculaC

你的label是不是+没有在M1上？看M1TXT是对的啊

DruculaC · 发表于 2012-3-17 11:23:33

回复 8# motofatfat

恩，确实是这个问题，要让+落在M1上才行。。。
多谢大家了！！

[求助] calibre lvs 报错

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