在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2287|回复: 2

[招聘] 和芯星通招聘Senior Ic Design Engineer和senior embedded Software Engineer

[复制链接]
发表于 2010-12-16 14:18:40 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

Position and Responsibility:

Position: IC Design Engineer

LocationShanghai

Headcount: 5

Report To: IC Design Manager

[/td][/tr]

Responsibility:

·
Digital circuit design and specification define

·
RTL coding and verification

  • Block level synthesis and whole chip synthesis
  • Back-end design related support
  • Pre-/Post-layout STA and simulation.
  • Chip bring up and validation
  • Support verification engineer in building test vector on ATE
  • Support PSV team in silicon test
[/td][/tr]

Education and skill requirements:

  • MSEE/MSCS Degree or equivalent
  • Well knowledgeable in digital/Analog circuit design and digital signal process
  • Be familiar with C/C++, Have experience in embedded software is a plus
  • Be familiar with standard CAD tools, such as VCS/NCverilog/ Design compiler
  • Knowledgeable in asic design/verification methodology
  • Excellent analytical and problem solving skills
  • Must be a self motivated, energetic individual who takes pride and ownership in their work.
  • Innovative thinking and team working spirit.
  • Be initiative, capable to analyze and learn
  • High team and result orientation are required.
  • Know how to share knowledge with other colleagues.
  • Fluent speaking and writing skills in English
[/td][/tr]


Position and Responsibility:

Position: Senior IC Design EngineerLocationShanghaiHeadcount: 5Report To: IC Design Manager
Responsibility:·
Block level Micro-architecture definition.
·
RTL coding and verification
  • Block level synthesis ,constraint generation and maintenance and whole chip synthesis support
  • Help on test plan development to guarantee IP fully tested.
  • Pre-/Post-layout STA and simulation.
  • Back-end design related support
  • Chip bring up and validation
  • Support verification engineer in building test vector on ATE
  • Support PSV team in silicon test
Education and skill requirements:
  • MSEE/MSCS Degree or equivalent
  • More than 3 years experience in hands-on ASIC design
  • Track record of 1+ successful tape-out of million-gates or above ASIC
  • Well knowledgeable in digital/Analog circuit design and digital signal process
  • Be familiar with C/C++, Have experience in embedded software is a plus
  • Be familiar with standard CAD tools, such as VCS/NCverilog/ Design compiler
  • Knowledgeable in ASIC design/verification methodology
  • Excellent analytical and problem solving skills
  • Must be a self motivated, energetic individual who takes pride and ownership in their work.
  • Innovative thinking and team working spirit.
  • Be initiative, capable to analyze and learn
  • High team and result orientation are required.
  • Know how to share knowledge with other colleagues.
  • Fluent speaking and writing skills in English

JD Senior Embedded Software Enginner.pdf (22.24 KB, 下载次数: 6 )



如果您有兴趣麻烦发简历到recruiting@unicorecomm.com,我们会尽快联系您 有任何问题我们也会给您解答~谢谢!

发表于 2010-12-16 22:49:17 | 显示全部楼层
我是做模拟的
发表于 2010-12-16 23:17:09 | 显示全部楼层
我是做数字的
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /3 下一条

×

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-4-20 07:06 , Processed in 0.025974 second(s), 11 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表