SynaptiCAD Product Suite v13.33a

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SynaptiCAD develops EDA tools that help engineers think criticallyabout their designs and offers a complete line of Vhdl and verilogmodel generation, simulation, and timing diagram visualization tools.SynaptiCAD's WaveFormer Lite is used to generate test benches fromsingle timing diagrams. The package can be upgraded to WaveFormer Proto add Analog Signal Display and Interactive simulation for creatingthe timing diagrams or TestBencher Pro to add multi-diagram test benchand reactive model generation. SynaptiCAD also offers VeriLoggerExtreme, a fast compiled Verilog simulator.

                               
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Product Suite:
WaveFormer Prois a revolutionary new rapid-prototyping EDA tool that helps you designfaster and with fewer mistakes. Upgrade WaveFormer Lite to WaveFormerPro and get analog signal display and digital timing analysis featurethat enables you to automatically determine critical paths, verifytiming margins, adjust for common delay effects, and perform "what if"analysis to determine optimum clock speed. WaveFormer Pro also lets youspecify and analyze system timing and perform RTL level simulationwithout the need for schematics or simulation models. When your timingdiagram is complete, you can then generate digital stimuli for yourfavorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Prohas the ability to import and annotate simulation and logic analyzerdata for publication-quality design documentation

                               
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TestBencher Proprovides designers with a graphical environment for rapidly generatingand testing bus-functional models for VHDL, Verilog, and SystemC. WhereWaveFormer Lite generates testbenches using one timing diagram,TestBencher allows multiple timing diagrams to be linked together togenerate bus functional models. Each timing diagram is a reusable bustransaction and they can be applied to the model under test using bothspecified and random data generation. TestBencher Pro dramaticallyreduces the time necessary to develop test suites by generating modelcode from language independent graphical timing diagrams and automatingthe build process.

                               
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VeriLogger Extremeis a completely new, high-performance compiled-code Verilog 2001simulator that significantly reduces simulation debug time. VeriLoggerExtreme offers fast simulation of both RTL and gate-level simulationswith SDF timing information. VeriLogger Extreme supports designlibraries and design flows for all major asic and FPGA vendors.VeriLogger Extreme also comes with BugHunter Pro, a graphicalVerilog/VHDL integrated development environment, which supportsdebugging with all major HDL simulators. BugHunter supportssource-level debugging, a waveform compression engine for high-speedwaveform dumping and viewing, and graphical test bench generationfeatures for rapidly testing HDL models.

                               
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