在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
查看: 738|回复: 0

[招聘] 上海公司DFT职位招聘AI研发和处理器研发

[复制链接]
发表于 2018-7-11 17:36:57 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

上海AI研发公司和处理器研发公司,DFT职位招聘,公司平台好,发展前景大,有兴趣联系,电话和微信18163979512,邮箱daisy.yang@hibohr.com


DFT工程师:

Job description

Perform and/or lead various DFT tasks for the creation of SOC chips. The main areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc. He will be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage.

Key Responsibilities:

• Architect DFT strategies for complex SOC designs

• Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc.

• Generate ATPG vectors for stuck-at, delay fault and other types

• Determine, analyze and enhance fault coverage to achieve target test quality

• Interface with ATE test engineer

Requirements:

•BS/MS in Electrical or Computer Engineering with 5+ years’related experience designing DFT for SOCs

•Expert level knowledge of DFT including scan, boundary scan, BIST, fault models and ATPG

•Strong working knowledge of SOC design and design methodology

•Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh

•Excellent RTL and gate level debug skills

•Strong experience with verilog RTL design and simulation

•Desirable: Previous use/experience with ATE

•Desirable: Formal analysis / STA Experience


您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

关闭

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-28 21:05 , Processed in 0.015820 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表