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A continuous-time delta-sigma modulator for 802.11a bg WLAN implemented with a hierarchical bottom-up optimization methodology
簡介：
This work presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2008-3-7 17:19:11
发表于 2008-3-13 19:56:11
