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Springer 2008新书 —— Standardized Functional Verification

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发表于 2008-1-7 23:37:00 | 显示全部楼层 |阅读模式

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Standardized Functional Verification_resize.jpg
Standardized Functional Verification

Wiemann, Alan

2008, XVII, 275 p., Hardcover
ISBN: 978-0-387-71732-6


Ships in 3 - 5 business days
$129.00


About this book
|
Table of contents

About this book
Standardized Functional Verification describes the science of functional verification that applies to any digital hardware system. With a precise and comprehensive terminology this book describes a thorough technical framework for achieving superior results with greater efficiency. It also defines a scientific basis for achieving functional closure and shows how true functional closure can be measured by software.

The author provides a wealth of practical guidance to the practicing professional. It describes how to compare results from differing projects and how to assess the risk of functional bugs at tape-out or at any other critical product juncture. The book also shows consumers how to compare IP offerings from multiple vendors. For producers, it describes how to verify IP in a manner that meets customer needs. Producers and consumers of silicon IP therefore have a solid framework to communicate requirements and to align expectations effectively and efficiently.

Standardized Functional Verification is a valuable reference for verification engineers and managers, and also for developers of verification software. The principles and theory this book describes will drive creation of the next generation of verification tools.

Written for:
Verification engineers, project managers
Keywords:
  • Digital Design
  • Functional Verification
  • Integrated Circuit


[ 本帖最后由 benemale 于 2008-1-7 23:47 编辑 ]

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 楼主| 发表于 2008-1-7 23:38:18 | 显示全部楼层
Creating Assertion-Based IP_resize.jpg
Creating Assertion-Based IP

Series: Series on Integrated Circuits and Systems

Foster, Harry D., Krolnik, Adam C.

2008, XVIII, 318 p., Hardcover
ISBN: 978-0-387-36641-8


This item usually ships in 2-3 business days
$129.00

About this book
|
Table of contents

About this book
  • Demonstrates a systematic process for formal specification and formal testplanning
  • Presents formal testplanning guidelines with examples focused on creating assertion-based verification IP
  • Details effective use of assertions languages beyond the traditional language construct discussions
Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:
  • modularity—assertion-based IP should have a clear separation between detection and action
  • clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations)

A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.
From the Foreword:

Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."

Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis


Written for:
Design and verification engineers; SoC/ASIC design project managers

Keywords:
  • Assertion-Based
  • Foster
  • IP
  • Krolnik
  • Verification
  • integrated circuits


[ 本帖最后由 benemale 于 2008-1-7 23:46 编辑 ]

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发表于 2008-1-8 08:59:18 | 显示全部楼层
发表于 2008-1-8 09:02:42 | 显示全部楼层
一贯的支持楼主贴好书!
发表于 2008-1-8 09:34:52 | 显示全部楼层
good!
发表于 2008-1-8 11:27:49 | 显示全部楼层
感谢搂主
发表于 2008-1-8 12:43:35 | 显示全部楼层
一贯的支持楼主贴好书
发表于 2008-1-8 14:30:47 | 显示全部楼层
benemale benemale benemale benemale benemale
发表于 2008-1-9 08:37:52 | 显示全部楼层
搂住哪来的这么多好书,太牛了!
发表于 2008-1-9 18:21:17 | 显示全部楼层
grateful to u!!!!
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