『三味书屋』元旦送礼之八：The Kluwer 2002～2004(数字部分)

benemale

『三味书屋』元旦送礼之一：Analog Circuit Design Series

『三味书屋』元旦送礼之二：Springer 2008新书s

『三味书屋』元旦送礼之三：The Kluwer 2002～2004(模拟部分)(A～E)

『三味书屋』元旦送礼之四：The Kluwer 2002～2004(模拟部分)(H～M)

『三味书屋』元旦送礼之五：The Kluwer 2002～2004(模拟部分)(O～W)

『三味书屋』元旦送礼之六：著名的Kluwer丛书系列 Volume 675～759

『三味书屋』元旦送礼之七：著名的Kluwer丛书系列 Volume 494～672

『三味书屋』元旦送礼之八：The Kluwer 2002～2004(数字部分)

『三味书屋』元旦送礼之九：著名的Kluwer丛书系列 Volume 435～703

[ 本帖最后由 benemale 于 2008-1-8 11:32 编辑 ]

benemale

	Advanced Verification Techniques  A SystemC Based Approach for Successful Tapeout Singh, Leena, Drucker, Leonard 2004, 395 p., Hardcover ISBN: 978-1-4020-7672-5 Ships in 3 - 5 business days
	$139.00

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About this book
"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages.  Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
                                                                                     - Stuart Swan
Written for:
Those is industry involved with functional verification of ASIcs.
Keywords:

• Singh

[ 本帖最后由 benemale 于 2008-1-7 22:28 编辑 ]

benemale

	Algorithms for VLSI Physical Design Automation Sherwani, Naveed A. 3rd ed., 1999, 608 p., Hardcover ISBN: 978-0-7923-8393-2 Ships in 3 - 5 business days
	$88.00

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About this textbook
Algorithms for VLSI Physical Design Automation, Third Edition covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concepts and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.
Algorithms for VLSI Physical Design Automation, Third Edition provides a comprehensive background in the principles and algorithms of VLSI physical design. The goal of this book is to serve as a basis for the development of introductory-level graduate courses in VLSI physical design automation. It provides self-contained material for teaching and learning algorithms of physical design. All algorithms which are considered basic have been included, and are presented in an intuitive manner. Yet, at the same time, enough detail is provided so that readers can actually implement the algorithms given in the text and use them.
The first three chapters provide the background material, while the focus of each chapter of the rest of the book is on each phase of the physical design cycle. In addition, newer topics such as physical design automation of FPGAs and MCMs have been included.
The basic purpose of the third edition is to investigate the new challenges presented by interconnect and process innovations. In 1995 when the second edition of this book was prepared, a six-layer process and 15 million transistor microprocessors were in advanced stages of design. In 1998, six metal process and 20 million transistor designs are in production. Two new chapters have been added and new material has been included in almost allother chapters. A new chapter on process innovation and its impact on physical design has been added. Another focus of the third edition is to promote use of the Internet as a resource, so wherever possible URLs have been provided for further investigation.
Algorithms for VLSI Physical Design Automation, Third Edition is an important core reference work for professionals as well as an advanced level textbook for students.

[ 本帖最后由 benemale 于 2008-1-7 22:57 编辑 ]

benemale

	The Verilog PLI Handbook    A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface Series: The Springer International Series in Engineering and Computer Science , Vol. 666 Sutherland, Stuart 2nd ed., 2002, 808 p. With CD-ROM., Hardcover ISBN: 978-0-7923-7658-3 This item usually ships in 2-3 business days
	$160.00

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About this book
The Verilog Programming Language Interface is a powerful feature of the Verilog standard. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired, such as adding custom design debug utilities, adding proprietary file read/write utilities, and interfacing bus functional C language models to a simulator.
This book serves as both a user's guide for learning the Verilog PLI, and as a comprehensive reference manual on the Verilog PLI standard. Both the TF/ACC ("PLI 1.0") and the VPI ("PLI 2.0") generations of the PLI are presented, based on the IEEE 1364 Verilog standard. The second edition of this book adds detailed coverage of the many enhancements added in the latest IEEE 1364-2001 Verilog standard ("Verilog-2001").
A CD is included, with the C source code, Verilog HDL test cases and simulation result logs for more than 75 complete PLI examples.
Written for:
Researchers, scientists

[ 本帖最后由 benemale 于 2008-1-7 23:10 编辑 ]

benemale

	Symbolic Analysis and Reduction of VLSI Circuits Qin, Zhanhai, Tan, Sheldon X.D., Cheng, Chung-Kuan 2005, XXII, 283 p., Hardcover ISBN: 978-0-387-23904-0 Ships in 3 - 5 business days
	$125.00

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About this book
Symbolic analysis is an intriguing topic in VLSI designs.
The analysis methods are crucial for the applications to the parasitic reduction and analog circuit evaluation. However, analyzing circuits symbolically remains a challenging research issue. Therefore, in this book, we survey the recent results as the progress of on-going works rather than as the solution of the field.
For parasitic reduction, we approximate a huge amount of electrical parameters into a simplified RLC network. This reduction allows us to handle very large integrated circuits with given memory capacity and CPU time. A symbolic analysis approach reduces the circuit according to the network topology. Thus, the designer can maintain the meaning of the original network and perform the analysis hierarchically.
For analog circuit designs, symbolic analysis provides the relation between the tunable parameters and the characteristics of the circuit. The analysis allows us to optimize the circuit behavior.

Written for:
Graduate students in electrical engineering, researchers and engineers in the fields of analog design and signal integrity
Keywords:

• analog circuit analysis
• linear circuit reduction
• parasitic reduction
• topological circuit analysis

[ 本帖最后由 benemale 于 2008-1-7 23:25 编辑 ]

benemale

	Fast, Efficient and Predictable Memory Accesses  Optimization Algorithms for Memory Architecture Aware Compilation Wehmeyer, Lars, Marwedel, Peter 2006, XI, 257 p., Hardcover ISBN: 978-1-4020-4821-0 This item usually ships in 2-3 business days
	$125.00

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About this book
The memory system is increasingly turning into a bottleneck in the design of embedded systems. The speed improvements of memory systems are lower than the speed improvements of processors, eventually leading to embedded systems whose performance is limited by the memory. This problem is known as the "memory wall" problem. Furthermore, memory systems may consume the largest share of the system’s energy budget and may be the source of unpredictable timing behaviour. Hence, the design of the memory system deserves an increasing amount of attention.
Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Written for:
Researchers and PhD students in the area of Computer Science, designers of Embedded Systems

Keywords:

• Compiler
• Embedded Systems
• Energy
• Memory
• Timing Predictability

[ 本帖最后由 benemale 于 2008-1-7 23:27 编辑 ]

benemale

	Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms Kogel, Tim, Leupers, Rainer, Meyr, Heinrich 2006, XIV, 199 p., Hardcover ISBN: 978-1-4020-4825-8 This item usually ships in 2-3 business days
	$119.00

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About this book
The drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification.

In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

Written for:
Researchers and professionals generally interested in ESL Design; researchers and professionals in the fields of MPSoC, NoC, and SoC modeling; modeling groups and system architects in Original Equipment Manufactures (OEMs) in the digital consumer, wireless communications, and office automation domain (e.g. Sony, Nokia, Motorola, Canon, OKI, Samsung), semiconductor companies and Intellectual Property (IP) providers (Philips, Infineon, ST Microelectronics, Texas Instruments, Toshiba, Intel, ARM, ESL tool developers and their customers (Synopsys, Cadence, Mentor Graphics, CoWare)

Keywords:

• Electronic System Level (ESL)
• Multi-Processor System-on-Chip (MP-SoC)
• Network-on-Chip (NoC)
• SystemC
• Transaction Level Modeling (TLM)

[ 本帖最后由 benemale 于 2008-1-8 14:27 编辑 ]

benemale

好了，吃饭去了。。。

icie

楼主的好东西就是多    爱死你了

chenxujin

Thanks for this document!