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发表于 2020-8-12 15:12:42
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显示全部楼层
对, example 如下。 后仿不带pg
#no pg, no physical only cells, and no supply statements
write_verilog -exclude {scalar_wire_declarations leaf_module_declarations end_cap_cells well_tap_cells filler_cells pad_spacer_cells physical_only_cells cover_cells pg_netlist supply_statements} -hierarchy all $OUTPUTS_DIR/${DESIGN_NAME}.v
#with pg, no physical_only cells, no diodes, and no supply statements
write_verilog -exclude {scalar_wire_declarations leaf_module_declarations end_cap_cells well_tap_cells filler_cells pad_spacer_cells physical_only_cells cover_cells diode_cells supply_statements} -hierarchy all $OUTPUTS_DIR/${DESIGN_NAME}.pg.v
#with pg, and with physical only cells
write_verilog -exclude {scalar_wire_declarations leaf_module_declarations empty_modules} -hierarchy all $OUTPUTS_DIR/${DESIGN_NAME}.phy.v
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