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不太理解source-synchronous和LVDS mode有啥区别,有大神能讲解一下么?
我查了下官方文档,它的说法如下
对于 source-synchronous mode:
1.
If you select the source synchronous mode, the clock
delay from pin to I/O input register matches the data
delay from pin to I/O input register | 2.
- Source Synchronous—Maintains the same data and clock timing relationship seen at the pins at any IOE register. Ideally, this mode compensates for the delay of the clock network used, plus any difference in delay between the following two paths:
而对于 LVDS mode:
1.
If you select the lvds mode, the same data and clock
timing relationship of the pins at the internal SERDES
capture register is maintained. Te mode compensates
for the delays in LVDS clock network, and between the
data pin and clock input pin to the SERDES capture
register paths. | 2.
- LVDS—Maintains the same data and clock timing relationship seen at the pins of the internal SERDES capture register. Ideally, this mode compensates for the delay of the LVDS clock network, plus any difference in delay between the following two paths:
不太理解这里的IOE register和serdes capture的区别
我目前用的是cyclone V GX的FPGA 5CGXFC5C6F27C7,目的是将ADC输出的13bit并行源同步输出(时钟400M)采集下来。我看datasheet里面说明是在每一个bank,都可以用差分pin做LVDS接口,且速度限制在500M左右,但是他自身在芯片的左侧是有12个高速收发器接口的,可以实现3G的bps。
我个人理解是,如果用GPIO接收的话就选择source-synchronous mode,如果用高速收发器接收的话,就选LVDS mode,请问对吗。第一次用FPGA做高速采集,完全是在瞎蒙,求助各位大神,谢谢
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