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楼主: jx87212

[求助] 上海浦西知名外企诚聘数字后端&DFT验证工程师,薪资40~80W

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 楼主| 发表于 2020-3-19 10:01:01 | 显示全部楼层

Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
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 楼主| 发表于 2020-3-20 09:54:49 | 显示全部楼层
Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
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 楼主| 发表于 2020-3-23 09:35:23 | 显示全部楼层
Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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 楼主| 发表于 2020-3-24 09:16:02 | 显示全部楼层
Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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 楼主| 发表于 2020-3-25 09:17:30 | 显示全部楼层

Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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 楼主| 发表于 2020-3-26 09:01:54 | 显示全部楼层


Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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 楼主| 发表于 2020-3-27 09:42:14 | 显示全部楼层

Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

使用道具 举报

 楼主| 发表于 2020-3-28 15:38:40 | 显示全部楼层
Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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 楼主| 发表于 2020-3-30 08:52:40 | 显示全部楼层

Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

使用道具 举报

 楼主| 发表于 2020-3-31 09:31:52 | 显示全部楼层

Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test

Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit
回复 支持 反对

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