Physical and Silicon Measures of Low Power Clock Gating Success: An Apple to Apple Case Study

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Table of Contents
1.0 Introduction..................................................................................................................................... 4
2.0 Implementation Details................................................................................................................... 5
2.1 Maximizing the benefits of clock gating ........................................................................................ 6
2.2 Other Portion of the Design Flow................................................................................................... 8
3.0 Results............................................................................................................................................. 9
3.1 Area Saving..................................................................................................................................... 9
3.2 Routing Improvement ................................................................................................................... 10
3.3 Switching Capacitance Improvement ........................................................................................... 12
3.4 Gated Capacitance Improvement in Clock Tree........................................................................... 13
3.5 Power Saving in Silicon................................................................................................................ 14
4.0 Conclusions and Recommendations ............................................................................................. 16
5.0 Acknowledgements....................................................................................................................... 16
6.0 References..................................................................................................................................... 17

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