时间交织ADC博士论文--伯克利2015年

IcRabia · 发表于 2019-7-22 09:29:07

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The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.

Design Techniques for Ultra-High-Speed Time-Interleaved ADC.pdf (2.62 MB, 下载次数: 539 )