为什么ICG中会莫名其妙多出一条内部的CKcheckpin1，而且还被工具识别为sink点？

巴甫洛夫很忙 · 发表于 2019-6-29 20:14:11

如题，用smic0.13um工艺做项目，CTS之后发现skew很大，达到了0.5，检查时钟树的结构发现ICG内部有一条名字叫做CKcheckpin1的pin被工具识别为sink点了，导致工具将ICG上的这条pin与它所驱动的寄存器作balance，skew变得很大，请问这种情况该怎么办？

巴甫洛夫很忙 · 发表于 2019-6-29 20:17:03

clock_tree summaey如下，其中clk_gen为clk的生成时钟

巴甫洛夫很忙 · 发表于 2019-6-29 20:19:39

检查时钟树，发现报了很多如下的warning，在waring的后面可以发现CKcheckpin1被识别为sink点了。
Warning: The phase delay skew of entrance pin pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_0__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/CK in clock clk_gen is 0.817, larger than the threshold 0.050.  (CTS-871)
      The smallest early delay internal sink: pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_0__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/CKcheckpin1 (early delay: -0.390 (type: SINK) )
      The largest late delay output pin: pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_0__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/ECK (late delay 0.428 (type: SINK) )

Warning: The phase delay skew of entrance pin pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_1__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/CK in clock clk_gen is 0.816, larger than the threshold 0.050.  (CTS-871)
      The smallest early delay internal sink: pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_1__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/CKcheckpin1 (early delay: -0.390 (type: SINK) )
      The largest late delay output pin: pulpino_i/axi_interconnect_i/axi_node_i/u_RESP_BLOCK_GEN_1__RESP_BLOCK/DW_ADDR_DEC/MASTER_ID_FIFO/cg_cell_0/TLATNTSCAX4/ECK (late delay 0.426 (type: SINK) )