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芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
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[招聘] 寻找创业同伴-汽车电子-背景强大-团队靠谱

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发表于 2019-6-23 22:43:27 | 显示全部楼层 |阅读模式

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本帖最后由 rolegend 于 2019-6-24 09:37 编辑

首先,介绍一下我们的背景及产品方向:

芯擎科技由吉利集团及安谋中国公司等共同出资成立,注册地为湖北省武汉经济开发区,在北京和上海设有分支机构。芯擎科技专注于设计、开发并销售先进的汽车电子芯片。湖北芯擎科技有限公司的成立有助于填补中国高端汽车芯片的空白、提升中国汽车芯片产业开发及设计能力。
(PS: 背景强大,市场不愁)

产品描述
Siengine系列车用处理器,采用最新的arm 的中央处理器核心和面向异构计算而精心设计的SoC系统架构,基于先进的半导体制成工艺,为下一代车载信息娱乐系统带来强大处理能力,从而能提供丰富的车内视听娱乐和更多个性化的辅助自动驾驶体验。同时,其独特的安全孤岛核心为系统提供了冗余和实时的保护,满足汽车芯片对安全更加严格的标准的要求。
(PS:产品蓝海,技术领先)


然后,介绍一下我们的团队:
团队成员都是职场老兵,拥有丰富的经验和过硬的技术。软件团队成员很多来自freescale,做公司产品如鱼得水。IC团队来自于服务器芯片设计公司,处理大规模负责芯片游刃有余。管理团队来自业界知名大厂,无论管理理念还是管理技术,都相当靠谱。目前公司仍处于创业初期,此阶段加入,前景还是相当不错的。
(PS:团队靠谱,前景光明)

最后,介绍一下开放的职位:

Job Title: Senior/staff asic design engineer
Location: Beijing/Shanghai
JobDescription      
As part of the SOC design team, the design engineer willmainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP orsubsystem design;
-RTL coding to verify against circuit implementation;  Perform integration into SOCs.
-Maintain the 3rd party IP from vendor and verifyfunctions by creating test cases.
-Assist with chip bring up and perform siliconfunctional / performance validation.
-Assist with backend team on perform place-and-route andtiming analysis of modules

Job Requirement  
- Master’s degree in electrical engineering, computerengineering or related technical fields
- Good background in C, verilog, SystemVerilog andverification methodology.
- A high-level of self-motivation and a proactive approachto solving problems.
- Knowledge and experience with Python/Tcl and Unix/Linux Makefile scripting strongly desired.
- A high-level of self-motivation and a proactive approach to solving problems.
- Familiar with AMBA AXI/AHB/APB spec.
- Familiar with the frontend ASIC design methodology/flow.

Solid knowledge in one of the following areais a plus:
-Knowledge of ARM GIC/SMMU/Coresight architecture;
-Knowledge or designexperience of GPU/VPU/DPU;
-Knowledge or designexperience of PCIE/USB/Ethernet/UFS/eMMC;
-SoC power management unit design

-SoC clock & reset controllerdesign

Job Title: Verification Engineer(Sr. Staff/Staff Engineer)

Responsibilities:
- Lead theverification process, decompose tasks for each team member
- Create test planand review with architecture/design team
- Create randomconstraint test bench based on the requirement
- Create random testcases and direct test cases to achieve coverage goals
- Debug test benchand RTL, report bugs and track bug status
- Work closely with architecture/designteam to identify problems
- low-powerverification
- performanceverification
- Finish verificationtasks on time

Qualifications:
Bachelor or abovewith 6~10+ years’ work experience

Skills and Knowledge:
- Proficient with SystemVerilog & UVM
- Expert in the useof Cadence/Synopsys verification tools
- verificationexperience on automotive chip is a great plus
- cpu/GPU/ISP/DDRarchitecture knowledge is a great plus
- high speedinterface protocol knowledge is a great plus: PCIe/USB3.1/Ethernet, etc.
- verificationexperience using Palladium/ZeBU is a great plus
- scriptinglanguages (Python, Perl, Makefile, …) isan additional plus
- C and ARMv8.xassembly code programming skill is an additional plus
- Good communicationskills
------------------------------------------------------------------------------------------
Job Title: DFT Senior engineer/Manager
JobDescription      
1. SoC DFT plan definition, signoff the SoC DFT design asthe expert in this domain.
2. Lead the DFT team to finish the DFTdesign, including: MBIST, Memory repair, Scan insertion & compression, Onchip clocking for at-speed test, boundary scan chain insertion
3. Provide test mode SDC to implementation team and supportthe SoC test mode timing closure
4. DFT pattern generation and simulation.Fault coverage data collection and improve.
5. Support DFT pattern bring up on ATE andprovide support of failure diagnose and yield improving

Job Requirement   
1. At least 5+ years experiences in DFT
2. Hand on experience of SoC DFT plan definitionScan Compression logic/MBIST logic/Boundaryscan chain insertion, pattern bring up and diagnose
3. Familiar with the Mentor or Synopsys tool flow
4. A high-level of self-motivation and a proactive approachto solving problems.

5. For manager title, peoplemanagement experience is preferred.

总结一下:背景强大,团队靠谱,欢迎加入!
有兴趣请发简历到:shuo.zhang@siengine.com


发表于 2019-7-30 11:35:02 | 显示全部楼层
帮顶,一直关注这家公司,可惜没合适的岗位。
发表于 2019-8-10 11:22:02 | 显示全部楼层
关注,看好
发表于 2019-9-19 14:01:09 | 显示全部楼层
nice,very well.
发表于 2019-10-16 09:31:53 | 显示全部楼层
需要兼职吗?
发表于 2019-11-19 18:39:07 来自手机 | 显示全部楼层
有版图就更好了
发表于 2020-7-20 18:38:52 | 显示全部楼层
thanks
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