芯片的PAD做完了,DRC报一个ESD的错,指向的全是ESD PMOS管子的Source。 这些Source全部连到VDD上了。
rule里面写了 @ DRC will exclude D/S/G connected to PWSTRAP.
那为什么还报错呢?
不知道如何解决。望高人指点
ESD.1g { @ Use thin oxide transistor for thin oxide power clamp and thin oxide I/O buffers;
@ Use thick oxide transistor for the thick oxide Power Clamp and thick oxide I/O buffers.
@ DRC only flag ((MOS INTERACT OD2) INTERACT SDI) connected to (MOS NOT INTERACT OD2).
@ DRC will exclude D/S/G connected to PWSTRAP.
NET AREA RATIO NSDk_HVMOS_SDI NSDk_LVMOS PSDk_LVMOS LV_GATEk PTAPk > 0
[!!AREA(NSDk_HVMOS_SDI)*!AREA(PTAPk)*(!!AREA(NSDk_LVMOS)+!!AREA(PSDk_LVMOS)+!!AREA(LV_GATEk))]
RDB ESD.1g.hv_n.rep NSDk_HVMOS_SDI NSDk_LVMOS PSDk_LVMOS LV_GATEk
NET AREA RATIO PSDk_HVMOS_SDI NSDk_LVMOS PSDk_LVMOS LV_GATEk PTAPk > 0
[!!AREA(PSDk_HVMOS_SDI)*!AREA(PTAPk)*(!!AREA(NSDk_LVMOS)+!!AREA(PSDk_LVMOS)+!!AREA(LV_GATEk))]
RDB ESD.1g.hv_p.rep PSDk_HVMOS_SDI NSDk_LVMOS PSDk_LVMOS LV_GATEk
}