在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
查看: 534|回复: 0

[招聘] 版图职位招聘北京上海成都

[复制链接]
发表于 2019-4-23 18:48:35 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
国内AI研发公司版图职位招聘,工作地点:北京、上海、成都。有兴趣欢迎联系我了解详情,微信 yy17cc,邮箱 daisy@hibohr.com

Layout Design Engineer
Position Overview:
1.Planning and leading layout projects.
2.Responsible for Block level/top level layout implementation meeting design constraints.
3.Responsible for Tapeout, DRC/LVS/ANT.
4.Candidate will be responsible for Analog layout design of advanced semiconductor technologies, such as 16nm, 7nm and beyond. This role requires a close working
5.Relationship with circuit design engineers to develop layout that push the boundaries of technology and physics in order to deliver best products in Digital Encrypted Currency and Artificial Intelligence area.
Desired Skills and Experience:
1.At least 5 years analog and mix-signal layout experience.
2.Experience on 16nm/7nm analog layout design and optimization.
3.Good understanding of CMOS and FinFet technologies (device physics, deep sub-micron effects and layout effects)
4.Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
5.Proficient in EDA tools used for layout design (e.g. virtuoso/OA for layout design L/XL/GXL, Calibre for DRC/LVS/DFM, StarRC/QRC for Extraction, tools for Electro-migration and IR Drop analysis)
6.Cripting language (SKILL/Perl/TCL) proficiency is also desirable.

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

关闭

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-28 19:30 , Processed in 0.016032 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表