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compile_simlib -language all -dir {/home/lq/xilinx_lib2} -simulator vcs_mx -simulator_exec_path {/EDA/vcs2013.06/bin} -library all -family all
INFO: [Vivado 12-4753] Extracting data from the IP repository...(this may take a while, please wait)...
INFO: [setup_ip_static_library-Tcl-23] Data extracted from repository. Inspected 348 IP libraries.
Compiling libraries for 'vcs_mx' in '/home/lq/xilinx_lib2'
Compiling verilog library 'secureip'... verilog library 'axi_bfm'...[1 error(s), 0 warning(s)]
compile_simlib: 2 error(s), 0 warning(s), 0.35 % complete
Compiling vhdl library 'unisim'... vhdl library 'unimacro'...[1 error(s), 0 warning(s)] vhdl library 'unifast'...[1 error(s), 0 warning(s)]
compile_simlib: 3 error(s), 0 warning(s), 0.71 % complete
Compiling verilog library 'unisim'... verilog library 'unimacro'...[1 error(s), 0 warning(s)] verilog library 'unifast'...[1 error(s), 0 warning(s)]
compile_simlib: 3 error(s), 0 warning(s), 1.06 % complete
Compiling verilog library 'simprim'...
Compiling verilog library 'v_smpte2022_56_rx_v5_0_7'...
compile_simlib: 1 error(s), 0 warning(s), 96.82 % complete
Compiling vhdl library 'floating_point_v7_1_3'...
compile_simlib: 1 error(s), 0 warning(s), 97.17 % complete
Compiling vhdl library 'sid_v8_0_10'...
compile_simlib: 1 error(s), 0 warning(s), 97.53 % complete
Compiling vhdl library 'tcc_encoder_3gpp_v5_0_11'...
。。。。。。。。。。。。。。。。。。。。。。。
Compiling vhdl library 'rs_decoder_v9_0_12'...
compile_simlib: 1 error(s), 0 warning(s), 100.00 % complete
***********************************************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: vcs_mx *
* Compiled on: Mon Dec 10 22:38:48 2018 *
。。。。。。。。。。。。。。。。。
*---------------------------------------------------------------------------------------------------------------------*
* lte_3gpp_channel_estimator_v2_0_12 | vhdl | lte_3gpp_channel_estimator_v2_0_12 | 1 | 0 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_fft_v2_0_12 | vhdl | lte_fft_v2_0_12 | 1 | 0 *
*---------------------------------------------------------------------------------------------------------------------*
* rs_decoder_v9_0_12 | vhdl | rs_decoder_v9_0_12 | 1 | 0 *
*---------------------------------------------------------------------------------------------------------------------*
ERROR: [Vivado 12-3591] compile_simlib failed to compile for vcs_mx with 293 errors.
compile_simlib: Time (s): cpu = 00:01:44 ; elapsed = 00:02:14 . Memory (MB): peak = 7067.391 ; gain = 266.344 ; free physical = 722 ; free virtual = 9632
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors. |
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