[芯原微电子]-SoC Position（design/verification/flow）

小芯 · 发表于 2018-11-19 11:17:36

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本帖最后由小芯于 2020-1-6 09:49 编辑

Position :
1. Engineer/Sr. Engineer of SoC Design
前端设计工程师/高级工程师
2. Sr. Engineer/Staff Engineer of SoC Verification
前端验证高级工程师/资深工程师
3. Engineer/Sr. Engineer of SoC FE Flow
前端流程工程师/高级工程师

欢迎自投或者推荐简历到邮箱：hr.resume@verisilicon.com

具体JD和公司介绍如下：

【 Engineer/Sr. Engineer of SoC Design】

- Responsibilities:
1. Play an important role in defining chip spec and devising chip architecture.
2. Develop challenging modules including module spec definition, macro architecture design, RTL coding, simulation and synthesis.
3. Carry out chip level verification or chip integration/implementation.
4. Help junior engineers to solve technical issues.
5. Support customers regarding chip applications.

-Requirements:
1. Bachelor degree or above in EE, 3+ years experience.
2. Good knowledge of some of the following general IP: cpu/dsp, AMBA, DDR/SDRAM, video (HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO.
3. Good skill in the field of digital circuit design, whole digital design flow and EDA tools;
4. Key member in at least one successfully silicon proven challenging project.
5. Fluent in both English and Chinese.
6. Self motivated, good communication skill and team work spirit.

【Sr. Engineer/Staff Engineer of SoC Verification】

-Responsibilities:
1. Understanding the expected functionality of designs.
2. Developing testing and regression plans.
3. Designing and developing verification environment.
4. Running RTL and gate-level simulations/regression.
5. Code/functional coverage development, analysis and closure.

-Requirements:
1. Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
2. Knowledge in asic/FPGA design process and verification tools/env ( UVM/OVM…).
3. Familiar with design and verification languages (verilog, System Verilog, SVA etc.).
4. Scripting and automation skills (tcl, perl, makefile etc) a plus.
5. Familiar with C/C++.
6. Knowledge of DDR/Video/arm/USB/PCIE , Low Power Verification with UPF and design experience is a plus.
7. Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
8. Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
9. Independent and self-managing.

【Engineer/Sr. Engineer of SoC FE Flow】

-Responsibilities:
1. Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.
2. Prepare the DFT plan for the SoC design.
3. SCAN/MBIST/BSD insertion and synthesize methodology for Flatten / Hierarchical design.
4. Pre/Post simulation for test patterns.
5. Cooperate with timing engineer for timing signoff (STA).
6. Analog IP test implementation and simulation.
7. Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.
8. Formal check of RTL and netlist.

-Requirements:
1. Bachelor's degree or above, major in EE, CS or relevant.
2. Above 5years work experience to the one with Bachelor's degree and above 3years with Master's degree is required for Senior Engineer position.
3. Skilled in SoC PPA, better for low power design.
4. Improve low test coverage to achieve higher coverage.
5. Skilled in csh/perl/tcl scripts.
6. Be familiar with concept of SoC and P&R physical implementation.
7. Fluent in both English and Chinese.
8. Good team work spirit.

公司工作氛围非常好，关心员工及其家庭，工作团队nice，给予员工充分的成长发展空间，
欢迎自投或者推荐简历到邮箱：hr.resume@verisilicon.com