发一篇超低功耗860uW全数字锁相环ADPLL的paper

alex_fd12 · 发表于 2018-8-16 11:54:44

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希望大家一起讨论一下ADPLL，我做的是低功耗方向的ADPLL。

a 860uw 2p1 to 2p7GHZ ADPLL.pdf (1.86 MB, 下载次数: 503 )

elwin_huxr · 发表于 2018-8-16 13:16:16

谢谢楼主分享

peterlin2010 · 发表于 2018-8-16 13:30:08

希望大家一起讨论一下ADPLL，我做的是低功耗方向的ADPLL。
alex_fd12 发表于 2018-8-16 11:54

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ultra low power ADPLL WPAN 2013

ultra low power ADPLL WPAN_slides.pdf (6.18 MB, 下载次数: 176 )

RF PLLs for frequency synthesis and modulation consume a significant share of
the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios.
Compared to analog PLLs , all-digital phase-locked loops ( ADPLLs ) are preferred in
nanoscale CMOS , as they offer benefits of smaller area, programmability, capability
of extensive self-calibrations, and easy portability. However, analog PLLs dominate
the ulp arena, since the time-to-digital converter ( TDC ) of an ADPLL has tradi-
tionally been power hungry. In this work [1], an ultra-low power 2.1 GHz – 2.7 GHz
fractional-N ADPLL is presented for wireless personal area network ( WPAN ) applica-
tions. A DTC -assisted snapshot TDC and a DC-coupled DCO buffer with a tunable
voltage transfer characteristic ( VTC ) are proposed to lower the power consumption.
The ADPLL prototype fabricated in TSMC LP 40 nm CMOS process consumes only
860 µW at 1 V supply, and has a measured rms jitter of 1.71 ps (integrated from
1k to 100MHz), leading to a state-of-the-art jitter 2 -power FoM of -236 dB. The
frequency modulation capability is also demonstrated with a 2 Mcps HS-OQPSK
modulation for IEEE 802.15.4 (ZigBee) and 1 Mbps GFSK for Bluetooth Smart. This
work presents the first-ever wireless ADPLL to break the 1mW barrier and consumes
at least five-times lower power compared to state-of-the-art ADPLLs . The presented
low-power techniques enable the adoption of ADPLLs in the emerging ultra-low-power