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[招聘] Graphics IP DV Engineer-GMHUB Module

发表于 2018-8-9 15:29:31 | 显示全部楼层 |阅读模式

We're hiring!! If you have interest, pls. send your updated resume to


  • Understand the architecture of the     graphics IP and functional block being designed
  • Build C/C++ model for simulation
  • Build test bench and monitors for     DUT
  • Compose test plan and validation     vectors to ensure functional completeness
  • Debug function/performance bugs of     graphics IP
  • Work with global Front-End design     team and physical design team for large scale ASIC chip physical     implementation
  • Focus on physical design of deep sub-micron     GPU chips including block level (full chip) floor planning, timing     closure, place&route, physical verification etc


  • Have in depth knowledge of entire     design process from Design specification, defining architecture,     micro-architecture, RTL design and functional verification, synthesis,     Physical Design, Timing closure, Tape-out, and post-Si debug.
  • Have hands-on experience in     Chiplevel Design/Integration activities.
  • Some Physical Design exposure     required.
  • Perform Synthesis and netlisting     tasks such as SDC Development, Scan Insertion, ECO implementation, Formal     Verification, etc.
  • Some exposure to DFT is a strong     plus.
  • Work with Physical Design team on     Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power     analysis, IO PAD placement, etc.
  • Should have expertise in: Cadence     RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of     datapath compilers is required.
  • Expertise in Perl and Tcl is a     must.
  • Knowledge of chip bus interfaces     such as AHB and various standard peripherals & interfaces is a plus.
  • Should be able to work closely     with RTL Designers and Backend Physical Design teams across multiple     sites.
  • Must have good communication &     Analytical thinking skills.
  • Should have proficiency in flow     development and scripting.
  • Should be able to Lead a team, and     provide Technical mentoring and guidance to junior engineers.


  • Master with at least 5 years or     Bachelor with at least 8 years working experience in ASIC area
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