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[招聘] 上海公司DFT职位招聘AI研发和处理器研发

[招聘] 上海公司DFT职位招聘AI研发和处理器研发

上海AI研发公司和处理器研发公司,DFT职位招聘,公司平台好,发展前景大,有兴趣联系,电话和微信18163979512,邮箱daisy.yang@hibohr.com


DFT工程师:

Job description

Perform and/or lead various DFT tasks for the creation of SOC chips. The main areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc. He will be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage.

Key Responsibilities:

• Architect DFT strategies for complex SOC designs

• Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc.

• Generate ATPG vectors for stuck-at, delay fault and other types

• Determine, analyze and enhance fault coverage to achieve target test quality

• Interface with ATE test engineer

Requirements:

•BS/MS in Electrical or Computer Engineering with 5+ years’related experience designing DFT for SOCs

•Expert level knowledge of DFT including scan, boundary scan, BIST, fault models and ATPG

•Strong working knowledge of SOC design and design methodology

•Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh

•Excellent RTL and gate level debug skills

•Strong experience with Verilog RTL design and simulation

•Desirable: Previous use/experience with ATE

•Desirable: Formal analysis / STA Experience


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电子书:《模拟对话》,共50卷,数百篇精品文章,下载即奖励400信元!

电子书:《模拟对话》,共50卷,数百篇精品文章,下载即奖励400信元!


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