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北京上海FPGA职位招聘,欢迎咨询,欢迎推荐,电话微信18163979512,邮箱daisy.yang@hibohr.com
Sr. FPGA Engineer Job description: 1. Develop and support FPGA design for SOC verification 2. Responsible for FPGA RTL coding, and migration from asic RTL to FPGA RTL 3. Responsible for FPGA synthesis/PR timing clean-up and bit file generation 4. Responsible for system and FPGA debug with signal probe tools Qualifications: 1. Bachelor or above degrees in EE/Communication/CS majors 2. Must have experiences in digital logic design with verilog/Vhdl...etc. 3. Must have experiences with Xilinx Vertex/Spartan products and familiar with FPGA synthesis flows and tools (ISE, Vivado, Synplify, Chipscope, Protolink…etc) 4. Experience with DDR3/arm/USB FPGA design is a plus. 5. Experience with HAPS is a plus. |