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##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: L2.lvs.report
layout NAME: /ee/bscourse2018/s201530271117/project/IC617/CSMC05_M3/L2.sp ('L2')
SOURCE NAME: /ee/bscourse2018/s201530271117/project/IC617/CSMC05_M3/L2.src.net ('L2')
RULE FILE: /ee/bscourse2018/s201530271117/project/IC617/CSMC05_M3/__calibre.xrc.lvs__
CREATION TIME: Tue Jun 19 22:03:10 2018
CURRENT DIRECTORY: /ee/bscourse2018/s201530271117/project/IC617/CSMC05_M3
USER NAME: s201530271117
CALIBRE VERSION: v2015.2_36.27 Wed Jul 1 10:06:07 PDT 2015
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Connectivity errors.
Warning: Unbalanced smashed mosfets were matched.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT L2 L2
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "?VDD" "?vdd"
LVS GROUND NAME "?VSS" "?GND" "?vss" "?gnd"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE NAMES TYPES SUBTYPES VALUES
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(NN) w w 0
TRACE PROPERTY mn(NN) l l 0
TRACE PROPERTY m(LN) w w 0
TRACE PROPERTY m(LN) l l 0
TRACE PROPERTY md(DN) w w 0
TRACE PROPERTY md(DN) l l 0
TRACE PROPERTY mn(NP) w w 0
TRACE PROPERTY mn(NP) l l 0
TRACE PROPERTY m(LP) w w 0
TRACE PROPERTY m(LP) l l 0
TRACE PROPERTY md(DP) w w 0
TRACE PROPERTY md(DP) l l 0
TRACE PROPERTY d(ND) a a 0
TRACE PROPERTY d(PD) a a 0
TRACE PROPERTY c(CP) c c 0
TRACE PROPERTY q(P1) a a 0
TRACE PROPERTY q(P2) a a 0
TRACE PROPERTY q(P3) a a 0
TRACE PROPERTY q(N1) a a 0
TRACE PROPERTY q(N2) a a 0
TRACE PROPERTY r(RW) w w 0
TRACE PROPERTY r(RW) l l 0
TRACE PROPERTY r(RN) w w 0
TRACE PROPERTY r(RN) l l 0
TRACE PROPERTY r(RP) w w 0
TRACE PROPERTY r(RP) l l 0
TRACE PROPERTY r(NY) w w 0
TRACE PROPERTY r(NY) l l 0
TRACE PROPERTY r(PY) w w 0
TRACE PROPERTY r(PY) l l 0
TRACE PROPERTY r(RL) w w 0
TRACE PROPERTY r(RL) l l 0
TRACE PROPERTY r(H1) w w 0
TRACE PROPERTY r(H1) l l 0
TRACE PROPERTY r(H2) w w 0
TRACE PROPERTY r(H2) l l 0
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Connectivity errors.
Warning: Unbalanced smashed mosfets were matched.
LAYOUT CELL NAME: L2
SOURCE CELL NAME: L2
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 14 14
Instances: 80 17 * MN (4 pins)
1 1 C (2 pins)
9 3 * R (2 pins)
------ ------
Total Inst: 90 21
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 13 13
Instances: 12 12 MN (4 pins)
1 1 C (2 pins)
2 2 R (2 pins)
1 1 _smn2b (5 pins)
------ ------
Total Inst: 16 16
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 9 net030
--- 2 Connections On This Net --- --- 2 Connections On This Net ---
-------------------------- --------------------------
C49(56.855,-50.775):pos ** missing connection **
** missing connection ** CC0:neg
--------------------------------------------------------------------------------------------------------------
2 Net 12 net13
--- 4 Connections On This Net --- --- 4 Connections On This Net ---
-------------------------- --------------------------
C49(56.855,-50.775):neg ** missing connection **
** missing connection ** CC0:pos
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 0 0
Nets: 13 13 0 0
Instances: 5 5 0 0 MN(NN)
7 7 0 0 MN(NP)
1 1 0 0 C(CP)
2 2 0 0 R(H1)
1 1 0 0 _smn2b
------- ------- --------- ---------
Total Inst: 16 16 0 0
o Statistics:
80 layout mos transistors were reduced to 14.
66 mos transistors were deleted by parallel reduction.
6 source mos transistors were reduced to 3.
3 mos transistors were deleted by parallel reduction.
8 parallel layout resistors were reduced to 1.
2 parallel source resistors were reduced to 1.
o Initial Correspondence Points:
Ports: VDD VSS vout cin2 cin1
o Matched Mosfets Which Have Been Unequally Reduced:
X58/M0(95.485,-25.125) MPM10<1>
X59/M3(103.655,-19.430) MPM10<2>
X59/M2(101.355,-19.430) ** missing smashed mosfet **
X59/M1(99.055,-19.430) ** missing smashed mosfet **
X59/M0(96.755,-19.430) ** missing smashed mosfet **
X58/M3(88.585,-25.125) ** missing smashed mosfet **
X58/M2(90.885,-25.125) ** missing smashed mosfet **
X58/M1(93.185,-25.125) ** missing smashed mosfet **
X56/M0(87.555,-19.430) MPM5<1>
X57/M3(97.785,-25.125) MPM5<2>
X57/M2(100.085,-25.125) ** missing smashed mosfet **
X57/M1(102.385,-25.125) ** missing smashed mosfet **
X57/M0(104.685,-25.125) ** missing smashed mosfet **
X56/M3(94.455,-19.430) ** missing smashed mosfet **
X56/M2(92.155,-19.430) ** missing smashed mosfet **
X56/M1(89.855,-19.430) ** missing smashed mosfet **
M3(33.950,-15.645) MPM6<1>
M30(77.650,-15.645) MPM6<2>
M29(75.350,-15.645) ** missing smashed mosfet **
M6(36.250,-15.645) ** missing smashed mosfet **
**************************************************************************************************************
DETAILED INSTANCE CONNECTIONS
LAYOUT NAME SOURCE NAME
**************************************************************************************************************
(This section contains detailed information about connections of
matched instances that are involved in net discrepancies).
--------------------------------------------------------------------------------------------------------------
C49(56.855,-50.775) C(CP) CC0 C(CP)
pos: 9 ** net030 **
neg: 12 ** net13 **
** 12 ** pos: net13
** 9 ** neg: net030
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total cpu Time: 0 sec
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