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[招聘] 【英伟达NVIDIA-上海】招聘资深IC后端工程师

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发表于 2018-4-23 11:00:29 | 显示全部楼层 |阅读模式

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联络方式:

邮箱:heatherl@nvidia.com

微信:Heather (qingyousong)

IC后端工程师(网表综合,形式验证)asicPD Engineer

工作职责:

1. Chipintegration and netlist generation

2. Synthesis

3. Netlistquality check

4. FormalVerification

5. Constraintscreation and validation, timing budget.

6. Co-workwith PR engineers to implement chip partition and floorplan

7. Workin conjunction with RR engineers to achieve timing closure for both partitionand full chip level

8. Achievespecial timing closure, such as io, test, clock etc.

9. Functioneco creation

10. Developand enhance entire timing closure flow from frontend (pre-layout) to backend(post-layout)

11.
Flowautomation development

12.Methodologyin any of above areas.

任职资格:

1. BSEE,MSEE is preferred

2. Projectexperience in IC design implementation

3. Coursestaken in circuit design, digital design

4. Hand-onexperience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) ispreferred


加分项:

1. Proficientuser of Perl or TCL is preferred

2. ExcellentEnglish communication skill

资深IC后端工程师
(布局布线)SeniorPhysical Design Engineer

工作职责:

A senior role in physical design for NVIDIA GPU andMobile chips Participate in various aspects of physical design, including fullchip floor planning, power/clock distribution, timing optimization, place &route, timing closure, power/signal integrity analysis, and physicalverification Troubleshoot a wide variety of design and flow complicated issues,and apply proactive intervention Collaborate with RTL, DFT and Circuitdesigners to ensure high quality of design implementation.

任职资格:

1. BSin Engineering or Science

2. Poweruser of EDA tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence(EDI/Innovus/Voltus) or Mentor (Olympus-SOC)

3. Experiencein Clock/Power Distribution, P&R, Timing closure, RC Extraction, andverification on advanced technology nodes

4. 3+years of experience in above areas

加分项:

1. MSin Engineering or Science

2. Knowledgein FinFET technology, circuit design, and package design

3.
Experiencein physical verification tools from Synopsys (ICV) or Mentor (Calibre)

4. Proficiencyin Perl, Python, TCL and Makefile scripts

联络方式:

邮箱:heatherl@nvidia.com

微信:Heather (qingyousong)

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