1.
Physical design and layout of high performance power integrated circuits. 2.
Top level layout floorplanning and die size optimization. 3.
Cost effective implementing of IC circuit blocks. 4.
Physical layout verification including DRC/LVS,etc. 5.
Interfacting with circuit designers, process engineers and maks designers during product development.
1.
负责高性能集成电路版图设计,模拟方向;
2.
顶层版图布局规划以及芯片面积优化;
3.
高效电路模块版图设计以及面积优化;
4.
负责集成电路版图验证,确保DRC/LVS通过;
5.
在设计和流片过程中,与IC设计工程师,工艺工程师以及工厂密切配合
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