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本帖最后由 NVHR 于 2018-3-6 21:43 编辑
工作地点：上海市浦东新区秋月路26号 投递邮箱：heatherl@nvidia.com 芯片设计工程师asic Design/Verification Engineer
工作职责：
- Micro-architecture definition forSystem-level modules (Reset, Fuse, Strap, In-silicon measurement, Floorsweep,etc…)
- RTL design, synthesis, timing andsilicon bring-up
- Unit-level and System-levelverification
- Chip level integration
任职资格：
- BS / MS in electrical / computerengineering and related.
- Familiar with verificationmethodology, tools and flow
- Understand frontend ASIC designflow including RTL design, synthesis and timing analysis
- Excellent analytical andproblem-solving skills
加分项：
- Broad knowledge with Videotechniques, SOC architecture and Computer architecture is a big plus
- Strong programming skills in C/C++and Perl is appreciated as a plus
- Fluent English (both written andspoken) and excellent communication skills
- Good team work spirit, easy tocooperate with team members
芯片验证工程师ASIC Verification Engineer (Clocks)
工作职责：
- Module-level or Chip-level logicdesign, synthesis, timing constraints, and silicon bring-up.
- Module-level or Chip-levelverification, both for function and test mode
- Methodology or Flow developmentfor above tasks.
任职资格：
- BS / MS in electrical / computerengineering and related.
- Understand ASICdesign/verification/implementation flow
- Familiar with design/verificationlanguages as C/C++, verilog or Vhdl
- Know industrial standard scriptinglanguage as Perl, or Python, TCL, Ruby
- Excellent analytical andproblem-solving skills
- Fluent English and excellentcommunication skills
- Good team work spirit, easy tocooperate with team members
加分项：
- Understand JTAG, DFT, or OCC is aplus
SOC设计工程师SOC Design Engineer
工作职责：
- Responsible for creating complexGPUs and SOCs and interface directly with unit-level, Physical Design, CAD,Package Design, Software, DFT and other teams
- Get involved with defining andcreating methodologies that create more efficient and flexible SOCs in future.
任职资格：
- BS or MS (preferred) in EE or CS
- Understand frontend ASICdesign/verification/implementation flow
- Excellent analytical andproblem-solving skills
- Strong coding skills in Perl orother industry-standard scripting languages
- Fluent English (both written andspoken) and excellent communication skills to interface with many groups andbuild consensus
- Good team work spirit, easy tocooperate with team members
加分项：
- Prior experience in implementingSystem-On-Chip is a plus
- Prior experience in RTL build anddesign automation is a plus
芯片功耗工程师ASIC Power Engineer
工作职责：
- Create a methodology/algorithm toevaluate power efficiency on high-level (architecture) designs.
- Support IP designers using thepower flow to do the power scrubbing work and improve their power efficiency onmicro-arch (ASIC) level.
- Understand and perform block leveland chip-level power analysis.
- Communicate/Cooperate with localand abroad teams with power-related projects.
- Co-work with power ARCH team/IPteam to evaluate new low-power technologies and improve chip power efficiency.
任职资格：
- MSEE/MSCS postgraduate.
- Experience in ASICdesign/verification, low power knowledge is a strong plus.
- Must be familiar with at least oneof the programming languages, C/C++ (preferred), Python, Perl.
- Excellent English writing/speakingskills are desired.
- Good communication skills.
工作地点：上海市浦东新区秋月路26号 投递邮箱：heatherl@nvidia.com |
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发表于 2018-3-6 17:02:14
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