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Systemverilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling
Chapter 1: Introduction to SystemVerilog...............................................................1
Chapter 2: SystemVerilog Declaration Spaces ........................................................7
Chapter 3: SystemVerilog Literal Values and Built-in Data Types.....................37
Chapter 4: SystemVerilog User-Defined and Enumerated Types .......................75
Chapter 5: SystemVerilog Arrays, Structures and Unions ..................................95
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions ................137
Chapter 7: SystemVerilog Procedural Statements..............................................169
Chapter 8: Modeling Finite State Machines with SystemVerilog......................207
Chapter 9: SystemVerilog Design Hierarchy.......................................................223
Chapter 10: SystemVerilog Interfaces..................................................................263
Chapter 11: A Complete Design Modeled with SystemVerilog..........................301
Chapter 12: Behavioral and Transaction Level Modeling .................................329
Appendix A: The SystemVerilog Formal Definition (BNF) ...............................355
Appendix B: Verilog and SystemVerilog Reserved Keywords...........................395
Appendix C: A History of SUPERLOG, the Beginning of SystemVerilog .......401
SystemVerilog_for_Design.pdf
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发表于 2018-2-23 07:15:03
