[招聘] 【Availink招聘】IC芯片后端工程师/Physical Design Engineer

AvailinkHR

意向沟通/申请岗位，请发送简历至elaine.wang@availink.com，收到简历我们将即刻与您联系。谢谢。

CompanyIntroduction: Availink Inc. is atechnology-driven fabless semiconductor company, focusing on the multimedia anddigital TV industries.  Availink Inc. isbacked by premiere financial institutions, with offices in China and the United States and with targetedconsumer markets around the world. By grouping a great team of professionals,building multiple product lines in fast growing markets, and attractingfirst-tier customers, Availink is positioned to grow into a significant playerin the field.   If you are a hands-on,results-oriented and energetic individual, and like to take this opportunity togrow and strive to achieve the best results, Availink will offer you achallenging and rewarding career.

   

Location:Beijing, China

Address:北京市朝阳区酒仙桥14号兆维工业园（地铁14号线将台站）

Position Tasks, Duties andResponsibilities

The asic Physical DesignEngineer will:

• Perform full synthesis (RTLsynthesis, place &route) of standard cell IC.

• Perform library, IP, and ICdesign service evaluation and selection.

• Complete third party IPintegration and ensure vendor guidelines are followed.

• Work with front-endengineers to resolve problems and achieve design closure.

• Adhere to establisheddesign methodology and contribute to its continuous improvement

• Use scripting languages,configuration management, batch processing, and other techniques to ensuredesign quality and minimize turnaround time

• Maintain linux sever and EDA tools.

Candidate Qualifications:

Candidatemust:

• Hold BSEE (MS preferred).

• Have minimum of 5 yearshands-on experience in full flow IC back-end physical design and verification

• Have completed hierarchicalIC projects experiencein40nm and below.

• Have the ability toindependently identify and resolve design, tool, and flow problems

• Be able to design andimplement physical design strategies and methodologies for deep submicrondesigns.

• Be able to complete blockand chip level tapeout quality LVS and DRC

• Familiarwith Linux environments, familiar with EDA tool.

Any of the following isbeneficial:

• STA constraint design

• Equivalence checking – RTLto gates, and gates to gates

Tasksinclude all aspects of the physical design flow such as:

• RTLsynthesis

• ICphysical design flow

• Floorplanningand power grid implementations

• Hierarchicaldesign partitioning

• Placementof standard cells

• Scaninsertion / scan chain reordering

• AnalogIP integration

• Powerand IR drop analysis

• Clocktree synthesis

• Routing

• Parasiticextraction

• Timingverification

• Timingimprovements for critical macro blocks

• Timingclosure

• Noiseanalysis

• DFManalysis and improvement

• SignoffLVS/DRC

• Implementationof post tapeout ECO changes