请教ISE布线不成功怎么解决1 signals are not completely routed

morning206

Release 14.2 - par P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Mon Jan 15 14:03:17 2018

1 signals are not completely routed.

WARNINGarHelpers:360 - Design is not completely routed.

   clk48M_180ps
WARNINGarHelpers:361 - There are 17 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   FPGA_CLK_BANK0_IBUF
   FPGA_CLK_BANK2_IBUF
   FPGA_CLK_BANK3_IBUF
   GCLK_1_IBUF
   SPI1_IBUF
   SPI4_IBUF
   SW<0>_IBUF
   SW<1>_IBUF
   SW<2>_IBUF
   SW<3>_IBUF
   SW<4>_IBUF
   SW<5>_IBUF
   SW<6>_IBUF
   SW<7>_IBUF
   TMR_IBUF
   UART_RX_IBUF
   UART_TX_IBUF

morning206

新加的程序
PROCESS ( CS,DACA)
   BEGIN
           if(CS 'EVENT AND CS = '1')then
                if(DACA='0')then
                 DACA(11 DOWNTO 0)<=DACC;
                else DACB(11 DOWNTO 0)<=DACC;
                end if;
                end if;
   END PROCESS;

morning206

综合到布线就出问题了 我用的14.2 各位大神求助 十万火急

morning206

语法错误 丢人  已解决