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综合通过了,但是实现出现了错误,还有致命的警告:
After a week working this problem the web case engineer concluded that when one builds a core out of context, black box attributes are generated which are to be pasted into the source with the component declaration. Then when I deselected the out of context selection, I failed to remove the black box attributes from my code. Nevertheless, the clock wizard put the black box attributes in the vho file whether the clock was built out of context or not. In that case I just removed the attributes even though they were included in the vho file. All the critical warnings went away.
一个经典的致命警告,一个是我不懂,另一个是vho文件我都不知道他在哪里。
Solution
This occurs because the IP is a black box in the design.
The generate_target command in the script above does not generate the DCP checkpoint for the IP core.
As a result, when opt_design is run, the black box in the Synthesis run is not resolved and remains a black box in opt_design.
This means that these errors are valid.
To correctly add the IP core to the design, the IP core needs to be synthesized using the synth_ip command.
See the modified script below with the key line in bold:# created on disk
create_project -in_memory -part xc7k70tfbg676-1 -force my_project
# read an IP customization
read_ip my_core.xci
# Generate all the output products
generate_target all [get_files *my_core.xci]
# Create a DCP for the IP
synth_ip [get_files *my_core.xci]
# Query all the files for this IP (optional)
get_files -all -of_objects [get_files *my_core.xci]
read_vhdl my_top.vhd
synth_design -top my_top
opt_design
一个经典的错误,他提供的方法好复杂,另外都不知道到底是什么情况。
跟black box干起来了,这都是什么错误啊,英文没看太懂。有大神给解释一下吗? |
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