在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
查看: 2038|回复: 5

[招聘] Cadence 上海/ 北京招聘大量前端设计工程师 / 后端设计工程师---2017.11月最新职位

[复制链接]
发表于 2017-11-2 10:48:33 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Cadence 上海/ 北京招聘大量前端设计工程师 / 后端设计工程师, 有意者请将简历发至541515639@qq.com, 邮件标题中请注明应聘职位,谢谢!

Senior/ Principal Front-end DesignEngineer

Location: SH/BJ


           Position Description:

Ø
Deliver/implement DDR/HBM IP. The engineershould be able to act as a strong team member and contributor. Exercisejudgment within generally defined practices and policies.


           Specific duties include:

Ø
Proficiency in logic design, simulation

Ø
Proficiency in verilog and its simulationenvironment

Ø
Good knowledge of IC design

Ø
At least seven year experience working ondigital IC development projects, excellent communication skills and the uncannyability to both lead and contribute in a cooperative team environment.


            Position Requirements:

Ø
Essential Qualifications: Must have BS degreewith 9~12+ years of applicable experience, MS degree with 7~10+ years ofapplicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics.

Ø
Essential that the individual demonstratesstrong communication, verbal and written.

Requires good communication skills in English.

Ø
Will have demonstrated successful completion of10+ design projects as an individual contributor

Ø
Familiar with JEDEC-DDR/HBM, DFI and AMBAprotocols and have DDR project design experience



Title: Principal/Lead Physical Design Engineer

Location: Shanghai


           Position Description:

Ø
Perform physical design implementation,including floor planning, power grid design, place and route, clock treesynthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Ø
The candidate will have the opportunity to workon many varieties of challenging designs, i.e. low power and high speed design.The responsibility includes participating in or leading next generation PHY IPphysical design, methodology and flow development.


           PositionRequirements:        

Ø
BSdegree with 5~10+ years of applicable experience, MS degree with 4~8+ years ofapplicable experience in electrical engineering, microelectronics. Experiencedwith asic design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues. Solid knowledgeon LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physicalverification, DFM. Successful track records of taping out complex,16nm/10nm/7nm chips. Automation and programming-minded, solid coding experiencein Makefile/Tcl/Tk/Perl. Self-motivated, able to work independently or as ateam player, excellent verbal and written communication skills in English.

 楼主| 发表于 2017-11-8 09:24:12 | 显示全部楼层
update
 楼主| 发表于 2017-11-9 15:13:44 | 显示全部楼层
update
 楼主| 发表于 2017-11-13 17:19:21 | 显示全部楼层
update
 楼主| 发表于 2017-11-18 22:32:56 | 显示全部楼层
update
 楼主| 发表于 2017-12-31 12:59:48 | 显示全部楼层
update
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

关闭

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-29 02:45 , Processed in 0.023126 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表