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asic Digital Design Engineer(design, implementation)
Location: Wuhan
Email: qyzhong@synopsys.com
Thisposition will be leading a global team to develop timing constrain validationand DFT validation platform for Synopsys leading edge interface IP.
PositionResponsibilities:
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Drive and work closely with RTL,implementation and methodology teams to establish a flow that brings the RTLand STA constraints into the in-house infrastructure for STA analysis
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Use the regression infrastructure toprovide feedback to the RTL team on the timing-cleanliness of the design andthe quality of the STA constraints themselves
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Participate in the discussions/reviewsof the regression results to improve the correct and efficiency of the flow
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Be responsible for ATPG patterngeneration with good DFT fault coverage
Requirements:
Must have BSEE in EE with 7+ yearsof relevant experience or MSEE with 5+ years of relevant experience in thefollowing areas:
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Demonstrates good communication skillsin both Mandarin and English
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Excellent skills in scripting andautomation
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Experiences with timing/Synthesisconstraints and floorplan-aware synthesis
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Knowledge of verilog and IC designdevelopment cycle
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Demonstrates good analysis andproblem-solving skills
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leadership experience, demonstratestrong desire to lead and drive for results
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Experiences and decent knowledge with DFTfault coverage analysis, tools and flow setup: Synopsys TetraMax, Z01X
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