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[招聘] 【Synopsys武汉】招数字设计工程师(RD expert, design implementation)

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发表于 2017-11-1 15:27:55 | 显示全部楼层 |阅读模式

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asic Digital Design Engineer(design, implementation)


Location: Wuhan


Email: qyzhong@synopsys.com


Thisposition will be leading a global team to develop timing constrain validationand DFT validation platform for Synopsys leading edge interface IP.  



PositionResponsibilities:


·
Drive and work closely with RTL,implementation and methodology teams to establish a flow that brings the RTLand STA constraints into the in-house infrastructure for STA analysis


·
Use the regression infrastructure toprovide feedback to the RTL team on the timing-cleanliness of the design andthe quality of the STA constraints themselves


·
Participate in the discussions/reviewsof the regression results to improve the correct and efficiency of the flow


·
Be responsible for ATPG patterngeneration with good DFT fault coverage



Requirements:


Must have BSEE in EE with 7+ yearsof relevant experience or MSEE with 5+ years of relevant experience in thefollowing areas:


·
Demonstrates good communication skillsin both Mandarin and English


·
Excellent skills in scripting andautomation


·
Experiences with timing/Synthesisconstraints and floorplan-aware synthesis


·
Knowledge of verilog and IC designdevelopment cycle


·
Demonstrates good analysis andproblem-solving skills


·
leadership experience, demonstratestrong desire to lead and drive for results


·
Experiences and decent knowledge with DFTfault coverage analysis, tools and flow setup: Synopsys TetraMax, Z01X


 楼主| 发表于 2017-11-27 11:22:18 | 显示全部楼层
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 楼主| 发表于 2018-8-28 09:57:46 | 显示全部楼层
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 楼主| 发表于 2018-11-13 10:21:17 | 显示全部楼层
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