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[招聘] 【Cadence 上海】招聘 数字后端工程师

[招聘] 【Cadence 上海】招聘 数字后端工程师

简历命名:姓名 - 学校 - 专业 - 学历 - 投递职位

1. Physical Design Engineer-数字后端设计工程师 (IPG)
Job Description Summary
Perform physical design implementation, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.

The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design,

Job Requirements
• BS degree with 2~3+ years of applicable experience, MS degree with 1~2+ years of applicable experience in electrical engineering, microelectronics.
•  Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
•  Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
• Successful track records of taping out complex, 65/40/28 nm SOC chips.
•  Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
•  Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.

2. Customer Engagement Engineer-数字后端客户工程师 (DSG)
Job Description
1. Will be involved in developing software tools for advanced chip design platforms.
2. The responsibilities also include engaging with customers in understanding their ASIC design requirements for nano-technology process nodes and assisting them in adopting Cadence design platform and helping them in performing successful tapeouts of their System-on-chip designs using the same.
3. The job will also involves presenting and demonstrating relevant Cadence technologies and carrying out product evaluations, workshops, training and competitive replacement campaigns.

Job Requirements
1.The candidates should have strong in-depth P&R design experience in COT or ASIC area.
2.Experience and ability to get solutions in Floor plan, Power Planning/Analysis, CTS, timing optimization/analysis, signal integrity and DFM issues (DRC & Antenna) is a MUST. Strong interest and understanding of design methodologies are required.
3.Need to have good knowledge on VDSM (40nm and below) processes issues.
4.Good verbal and written presentation are must.
5. Hands-on Cadence Encounter experience is a big plus.
6.Minimum master degrees in EE or CS.


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